| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 261 | Error detection and offset cancellation during multi-wire communication | US12920806 | 2009-02-19 | US08462891B2 | 2013-06-11 | Jade M. Kizer; John Wilson; Lei Luo; Frederick Ware; Jared L. Zerbe |
| Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition. | ||||||
| 262 | Method and Arrangement for Conveying Additional Bits in a Communication System | US13381612 | 2011-10-18 | US20130094605A1 | 2013-04-18 | Erik Larsson |
| Methods and nodes in a communication system for conveying N additional bits with a block of data. A method in an encoding node involves determining (302) the respective value of the N additional bits, and selecting (304) a code based on the N values. The block of data is then encoded (306) by use of the selected code. A method in a decoding node involves determining (510, 608) which code, from a predetermined set of candidate codes associated with different possible combinations of values of the N additional bits, that was used for encoding the block of data. The respective values of the N additional bits are then determined based on the determined code. The methods and nodes enable that the N additional bits may be conveyed and determined in the decoding node in an efficient way, without decoding the block of data and at low computational complexity. | ||||||
| 263 | Memory controller and memory system including the same having interface controllers generating parity bits | US12758103 | 2010-04-12 | US08423878B2 | 2013-04-16 | WooSeong Cheong; Bumseok Yu; Chanho Yoon |
| A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block. | ||||||
| 264 | Memory Device And Method Of Storing Data With Error Correction Using Codewords | US13625554 | 2012-09-24 | US20130019143A1 | 2013-01-17 | Kwang Soo Seol; Sung-Il Park; Kyoung Lae Cho; In-sung Joe |
| Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. | ||||||
| 265 | Receiving circuit | US12289737 | 2008-11-03 | US08345805B2 | 2013-01-01 | Takeshi Hashimoto; Kazuhiro Ishida |
| A receiving circuit includes a frame memory to store received data of one frame, a de-rate matching circuit to generate data before encoding by reading the received data from the frame memory and performing de-rate matching in a reverse manner to rate matching performed on the received data at a transmitting end, and a TTI memory to store the data before encoding. | ||||||
| 266 | Low-power predecoding based viterbi decoding | US12538631 | 2009-08-10 | US08230313B2 | 2012-07-24 | Rami Abdallah; Seok-Jun Lee; Manish Goel |
| In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value. | ||||||
| 267 | System and method for joint source-channel encoding, with symbol, decoding and error correction | US11798175 | 2007-05-10 | USRE43231E1 | 2012-03-06 | Khalid Sayood; Michael W. Hoffman; Billy D. Pettijohn |
| Disclosed is a A system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder structure. | ||||||
| 268 | High data throughput turbo product encoder | US11897367 | 2007-08-30 | US08065585B1 | 2011-11-22 | Ayyoob Abbaszadeh; David Todd Wilstead |
| A source controller provides a block of n×a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nth row of information bits followed by the nth row FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle. | ||||||
| 269 | QUANTIZED CHANNEL STATE INFORMATION PREDICTION IN MULTIPLE ANTENNA SYSTEMS | US13190354 | 2011-07-25 | US20110280324A1 | 2011-11-17 | Bartosz Mielczarek; Witold A. Krzymien |
| A CSI vector quantizer (VQ) system is provided for time-correlated channels. The VQ system operates a receiver forwarding quantized channel state information in the form of indices and a transmitter predicting channel state change. The VQ system is aimed at feedback channels, in which bit errors, erasures and delays can occur. The VQ system uses transmitter-side channel prediction algorithms that work with the quantized CSI information and allow the system to recover from feedback channel transmission errors, erasures and delays. Moreover, the techniques can be used to lower the required feedback rate, while keeping the system's throughput at the required level. | ||||||
| 270 | MULTI-TIERED QUANTIZATION OF CHANNEL STATE INFORMATION IN MULTIPLE ANTENNA SYSTEMS | US13083375 | 2011-04-08 | US20110274182A1 | 2011-11-10 | Bartosz Mielczarek; Witold A. Krzymien |
| A multi-tiered CSI vector quantizer (VQ) is provided for time-correlated channels. The VQ operates by quantizing channel state information by reference to both the current channel state information and a prior channel state quantization. A system is also provided that uses multi-tiered CSI quantizers. Enhanced signaling between the transmitter and receivers is provided in order to facilitate the use of multi-tiered CSI quantizers. | ||||||
| 271 | Method and apparatus for evaluating performance of a read channel | US13007004 | 2011-01-14 | US08046669B2 | 2011-10-25 | Nils Graef; Zachary Keirn |
| Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | ||||||
| 272 | Multi-tiered quantization of channel state information in multiple antenna systems | US11852240 | 2007-09-07 | US08036282B2 | 2011-10-11 | Bartosz Mielezarek; Witold Krzymien |
| A multi-tiered CSI vector quantizer (VQ) is provided for time-correlated channels. The VQ operates by quantizing channel state information by reference to both the current channel state information and a prior channel state quantization. A system is also provided that uses multi-tiered CSI quantizers. Enhanced signaling between the transmitter and receivers is provided in order to facilitate the use of multi-tiered CSI quantizers. | ||||||
| 273 | Auxiliary path iterative decoding | US11775748 | 2007-07-10 | US08006172B2 | 2011-08-23 | Keith G. Boyer; Jin Lu; Mark Hennecken |
| A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory. | ||||||
| 274 | ENCODING DEVICE, CONTROLLER AND SYSTEM INCLUDING THE SAME | US13012304 | 2011-01-24 | US20110185267A1 | 2011-07-28 | Ki-Jun LEE; Jun-Jin KONG; Hong-Rak SON; Hyung-June KIM; Dong-Joon SHIN; Sung-Han JUNG; Sung-Rae KIM |
| An encoding device includes an encoder and a puncturing unit. The encoder generates parity bits based on information bits. The puncturing unit punctures the parity bits based on a puncturing pattern complying with a first criterion determining a period of the puncturing pattern and a second criterion determining positions of remaining parity bits. | ||||||
| 275 | Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes | US12604773 | 2009-10-23 | US07956772B2 | 2011-06-07 | Mohammad Amin Shokrollahi; Michael Luby |
| A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of encoded symbols are generated from a set of input symbols including source symbols and redundant symbols, wherein the input symbols are organized such that at least one of the input symbols is not used for a first encoding process, so that it is permanently inactivated for the purposes of scheduling a decoding process. A method of decoding data is also provided, wherein encoded symbols generated from a set of input symbols are used to recover source symbols, wherein the input symbols are organized such that at least one of the input symbols is not used for a first decoding process, so that it is permanently inactivated for the purpose of scheduling the decoding process. | ||||||
| 276 | Method and Apparatus for Evaluating Performance of a Read Channel | US13007004 | 2011-01-14 | US20110119566A1 | 2011-05-19 | Nils Graef; Zachary Keirn |
| Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | ||||||
| 277 | Systems and Methods for Retimed Virtual Data Processing | US12540283 | 2009-08-12 | US20110041028A1 | 2011-02-17 | Jingfeng Liu; Hongwei Song |
| Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples | ||||||
| 278 | Method and System for Decoding Low Density Parity Check Codes | US12510899 | 2009-07-28 | US20110029756A1 | 2011-02-03 | Eric Biscondi; David Hoyle; Tod David Wolf |
| A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded. | ||||||
| 279 | ENCODING AND DECODING DATA | US12473161 | 2009-05-27 | US20100306621A1 | 2010-12-02 | Bruce M. Cassidy |
| The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operations on the data units resulting in encoded symbols Sn, where n is a positive integer. | ||||||
| 280 | COMMON BROADCAST RECEIVER AND METHOD FOR PROCESSING A RECEIVED SIGNAL THEREOF | US12604441 | 2009-10-23 | US20100220779A1 | 2010-09-02 | Yong-sik KWON; Hae-joo JEONG; June-hee LEE |
| A common broadcast receiver that receives cable broadcast, terrestrial broadcast, and mobile broadcast signals is provided. The common broadcast receiver includes a synchronizer for receiving any one of a cable broadcast signal, a terrestrial broadcast signal, and a mobile broadcast signal including a training signal generated by a Deterministic Trellis Reset (DTR) and inserted in a data region, and synchronizing the received broadcast signal; and a signal detector for detecting any one of the cable broadcast signal, the terrestrial broadcast signal, and the mobile broadcast signal from the synchronized broadcast signal. Hence, the mobile broadcast signal can be received and processed in addition to the cable broadcast signal and the terrestrial broadcast signal. | ||||||
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