| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | OPTIMAL PERIOD RATE MATCHING FOR TURBO CODING | US14522257 | 2014-10-23 | US20150046778A1 | 2015-02-12 | Ba-Zhong Shen; Tak K. Lee |
| Optimal period rate matching for turbo coding. A means is provided herein by which a nearly optimal (e.g., optimal for one block size and sub-optimal for others) periodic puncturing pattern that depends on a mother code. Any desired rate matching can be achieved using the means and approaches presented herein to ensure an appropriate rate of an encoded block output from a turbo encoder so that the subsequently modulated signal generated there from has the appropriate rate. In addition, some embodiments can also employ shifting for another design level available in accordance with puncturing employed to provide for periodic rate matching. Selectivity can also be employed, such that, a first periodic puncturing pattern can be applied at a first time to ensure a first rate, and a second periodic puncturing pattern can be applied at a second time to ensure a second rate. | ||||||
| 182 | QUANTIZED CHANNEL STATE INFORMATION PREDICTION IN MULTIPLE ANTENNA SYSTEMS | US14193844 | 2014-02-28 | US20140247736A1 | 2014-09-04 | Bartosz Mielczarek; Witold Krzymien |
| A CSI vector quantizer (VQ) system is provided for time-correlated channels. The VQ system operates a receiver forwarding quantized channel state information in the form of indices and a transmitter predicting channel state change. The VQ system is aimed at feedback channels, in which bit errors, erasures and delays can occur. The VQ system uses transmitter-side channel prediction algorithms that work with the quantized CSI information and allow the system to recover from feedback channel transmission errors, erasures and delays. Moreover, the techniques can be used to lower the required feedback rate, while keeping the system's throughput at the required level. | ||||||
| 183 | Processing transmissions in a wireless communication system | US12667142 | 2008-06-20 | US08654894B2 | 2014-02-18 | Edward Andrews; Carlo Luschi; Jonathan Wallington |
| Disclosed herein are methods of processing transmissions in a wireless communication system to detect whether a transmission unit contains transmitted data, systems for processing transmissions in a digital communications system to detect the same, receivers for processing transmissions in a wireless communications system and computer readable media implementing a method for processing the same. In one embodiment, a method of processing transmissions in a wireless communication system to detect whether a transmission unit contains transmitted data includes: generating an averaged function of bit reliability indicators from a plurality of received samples and applying a test to compare an average of ln cosh(·) (natural logarithm of the hyperbolic cosine) values for the reliability indicators, with a factor proportional to an average signal-to-disturbance ratio of the plurality of samples to determine if the transmission unit contains transmitted data. | ||||||
| 184 | Bit error concealment methods for speech coding | US11111821 | 2005-04-22 | US08620651B2 | 2013-12-31 | Juin-Hwey Chen |
| A method of concealing bit errors in a signal is provided. The method includes decoding an encoded signal parameter based upon constraints placed on a signal parameter, comparing the decoded signal parameter against the constraints, and declaring the decoded signal parameter invalid when the constraints are violated. | ||||||
| 185 | Data Processing System with Failure Recovery | US13465214 | 2012-05-07 | US20130297983A1 | 2013-11-07 | Chung-Li Wang; Lei Chen; Fan Zhang; Shaohua Yang; Johnson Yen |
| Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors. | ||||||
| 186 | Memory device and method of storing data with error correction using codewords | US13625554 | 2012-09-24 | US08543892B2 | 2013-09-24 | Kwang Soo Seol; Sung-Il Park; Kyoung Lae Cho; In-Sung Joe |
| Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. | ||||||
| 187 | Systems and methods for retimed virtual data processing | US13570050 | 2012-08-08 | US08413020B2 | 2013-04-02 | Jinfeng Liu; Hongwei Song |
| Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. | ||||||
| 188 | Encoding and decoding data using store and exclusive or operations | US12473161 | 2009-05-27 | US08365053B2 | 2013-01-29 | Bruce M. Cassidy |
| The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operations on the data units resulting in encoded symbols Sn, where n is a positive integer. | ||||||
| 189 | Systems and Methods for Retimed Virtual Data Processing | US13570050 | 2012-08-08 | US20120324307A1 | 2012-12-20 | Jinfeng Liu; Hongwei Song |
| Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. | ||||||
| 190 | Memory device and method of storing data with error correction using codewords | US12453814 | 2009-05-22 | US08301978B2 | 2012-10-30 | Kwang Soo Seol; Sung II Park; Kyoung Lae Cho; In Sung Joe |
| Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. | ||||||
| 191 | Error correcting device, method, and program | US11999446 | 2007-12-04 | US08108752B2 | 2012-01-31 | Keisuke Tanaka |
| A device, method, and program are provided to prevent an increase of the probability of erroneous correction for a burst error having a length exceeding detection capability even if high correction capability is selected for a random error. In one embodiment, an apparatus corrects errors in a product code block including C1 codes in a row direction and C2 codes in a column direction. First, a C1 decoder performs C1 correction for each of an even C1 including even-numbered bytes in the C1 code and an odd C1 including odd-numbered bytes in the C1 code. Next, a C2 decoder performs erasure correction in C2 correction in the case where any one of the C1 correction results for the even C1 and the odd C1 is correction failure, and where one of the results is the 3-byte correction while the other one is the correction failure or the 3-byte correction. | ||||||
| 192 | Method and apparatus for adapting data to a transport unit of a predefined size prior to transmission | US11988294 | 2006-06-19 | US08046671B2 | 2011-10-25 | Peter Farkas |
| An apparatus and a method for adapting data in a communications system to be transmitted from a sender to a receiver, to a transport unit of a predefined size involve representing said data as a combination of bits over a finite field, wherein said data comprises of an information part and a control part; adapting said represented data to fit said predefined size of said transport unit, by expressing both said information and control parts with bits, wherein said bits are less in number that said represented combination of bits and a number of removed bits is known to said receiver, said removed bits comprise of bits from both said information and control parts. | ||||||
| 193 | METHODS AND APPARATUS FOR COMPUTING SOFT DATA OR LOG LIKELIHOOD RATIOS FOR RECEIVED VALUES IN COMMUNICATION OR STORAGE SYSTEMS | US12751966 | 2010-03-31 | US20110246859A1 | 2011-10-06 | Erich F. Haratsch; Nenad Miladinovic; Andrei Vityaev |
| Methods and apparatus are provided for computing soft data or log likelihood ratios for received values in communication or storage systems. Soft data values or log likelihood ratios are computed for received values in a communication system or a memory device by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the soft data value or log likelihood ratio using the set of parameters associated with the identified segment. The computed soft data values or log likelihood ratios are optionally provided to a decoder. | ||||||
| 194 | Quantized channel state information prediction in multiple antenna systems | US11852206 | 2007-09-07 | US08009778B2 | 2011-08-30 | Bartosz Mielczarek; Witold Krzymien |
| A CSI vector quantizer (VQ) system is provided for time-correlated channels. The VQ system operates a receiver forwarding quantized channel state information in the form of indices and a transmitter predicting channel state change. The VQ system is aimed at feedback channels, in which bit errors, erasures and delays can occur. The VQ system uses transmitter-side channel prediction algorithms that work with the quantized CSI information and allow the system to recover from feedback channel transmission errors, erasures and delays. Moreover, the techniques can be used to lower the required feedback rate, while keeping the system's throughput at the required level. | ||||||
| 195 | Method and apparatus for evaluating performance of a read channel | US12750049 | 2010-03-30 | US07941732B2 | 2011-05-10 | Nils Graef; Zachary Keirn |
| Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | ||||||
| 196 | Multi-channel communication method and apparatus using plural Markov Chain Monte Carlo simulations | US11593899 | 2006-11-06 | US07848440B2 | 2010-12-07 | Behrouz Farhang Boroujeny; Peiman Amini |
| A technique for estimating channel data probability in a multi-user or multiple-input multiple-output communication system is disclosed. The technique uses parallel Markov Chain Monte Carlo simulation to select a plurality of hypothetical channel data patterns. Channel data bit probabilities are obtained by summing conditional bit probabilities, where the conditional bit probabilities are conditioned on an observation of the multi-channel signal and the hypothetical channel data patterns. | ||||||
| 197 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME | US12758103 | 2010-04-12 | US20100306631A1 | 2010-12-02 | WooSeong Cheong; Bumseok Yu; Chanho Yoon |
| A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block. | ||||||
| 198 | METHOD FOR ASSIGNING AND UTILIZING FORWARD ERROR CORRECTING (FEC) CODES | US12415596 | 2009-03-31 | US20100251070A1 | 2010-09-30 | Sanjay G. Desai; Kevin G. Doberstein; Harish Natarahjan |
| An assignment scheme exploits the Media Access Control (MAC) layer protocol features under various MAC layer call scenarios. In one embodiment, the Hamming distance between pairs of critical Data Units are assigned to codewords with a minimum distance of dmin2=8 bits, thereby increasing the hard decision error correcting capability from 1 bit to 3 bits when deciding between these pairs of Data Units. The method for assigning data unit identification (DUID) codes by a radio operating within a wireless communication system includes determining by the radio whether an expected burst is a 4 Voice Burst with Encryption Synchronization Signaling (4V); when the expected burst is 4V, decoding the DUID within the received burst using an increased minimum distance; and when the expected burst is not 4V, decoding the DUID within the received burst using a minimum distance. | ||||||
| 199 | Fast error-correcting of embedded interaction codes | US11142844 | 2005-05-31 | US07729539B2 | 2010-06-01 | Zhouchen Lin; Qiang Wang; Jian Wang |
| A fast decoding technique for decoding a position of a bit in a pattern provided on a media surface that can generate large amounts of solution candidates quickly by switching or flipping bits and utilizing a recursion scheme. The fast decoding technique may be employed to simultaneously decode multiple dimensions of a pattern on the media surface. | ||||||
| 200 | LOW-POWER PREDECODING BASED VITERBI DECODING | US12538631 | 2009-08-10 | US20100034325A1 | 2010-02-11 | Rami Abdallah; Seok-Jun Lee; Manish Goel |
| In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value. | ||||||
QQ群二维码
意见反馈
意见反馈