141 |
Managing integrity of framed payloads using redundant signals |
US15622039 |
2017-06-13 |
US10103842B2 |
2018-10-16 |
Sergio Licardie; Rishipal Arya; Robert Brown |
A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network. |
142 |
METHOD FOR OPTIMISING THE TRANSMISSION OF VIDEO DATA STREAMS IN A WIRELESS NETWORK |
US15760435 |
2016-09-15 |
US20180262778A1 |
2018-09-13 |
Pierre KEIFLIN; Christophe CARNIEL; Daniel DEDISSE |
The invention relates to a method for improving the reliability and the reception quality of video data streams over a wireless network controlled by Wi-Fi communication protocols, the video data stream being encoded in the form of packets Q each including K first data blocks and H redundancy blocks for forward error correction (FEC), said stream comprising a series of packets G each including K+N blocks which are transmitted by at least one transmitting device multicasting same to client viewing devices such as smartphones. Said method includes the following steps, implemented by the client device for each of the data packets G received from the one or more transmitting devices: a/ monitoring the correct reception of the K first data blocks, decoding and viewing the video stream if the result is positive; b/ if all of the K first data blocks are not received, decoding if possible by means of a forward error correction (FEC) algorithm; c/ if the total number X of K+N blocks received is lower than K or if a positive result is not obtained from the preceding decoding step, sending a message regarding the one or more lost blocks; d/ if a statistical algorithm of the transmitting device organises the resending of the missing data, checking reception of data according to a/ and b/, decoding and viewing the video stream if the result is positive. |
143 |
PATH SORT TECHNIQUES IN A POLAR CODE SUCCESSIVE CANCELLATION LIST DECODER |
US15959012 |
2018-04-20 |
US20180241504A1 |
2018-08-23 |
Zahir Raza; Kevin A. Shelby |
Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both ûφ=0 and ûφ=1 bit estimate (LLR) updates based on the row from which the updated row will be derived. |
144 |
COMMUNICATION DEVICE, COMMUNICATION SYSTEM, COMMUNICATION METHOD AND PROGRAM |
US15739461 |
2016-04-25 |
US20180183617A1 |
2018-06-28 |
Hiroyuki Fukada; Takahiro Furuya |
A communication device includes: a function of receiving an information packet transmitted from a base station; a communication function of connecting to a local network for sharing information among a plurality of terminals; a function of generating a parity packet; a function of multicasting the generated parity packet and identification information of all source packets to the local network; a function of receiving the parity packet multicast by other terminals and the identification information of all source packets via the local network; a function of storing the received parity packet and the identification information of all source packets in a storage unit; and a function of recovering a lost packet using the parity packet and the identification information of all source packets. |
145 |
Systems and methods for last written page handling in a memory device |
US15195900 |
2016-06-28 |
US09928139B2 |
2018-03-27 |
Zhengang Chen; Yu Cai; Erich F. Haratsch; Zhimin Dong |
Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells. |
146 |
Method and apparatus for processing a downlink shared channel |
US14687858 |
2015-04-15 |
US09698959B2 |
2017-07-04 |
Nader Bolourchi; Stephen E. Terry; Stephen G. Dick |
A method and apparatus is disclosed in which a user equipment (UE) receives and processes control information received on a first channel. In accordance with a particular embodiment, a use equipment (UI) having a user equipment processor coupled with user equipment circuitry includes means for receiving, via the user equipment circuitry, a wireless signal of a control channel; in which the wireless signal includes both (i) an N bit field and (ii) control information, the N bit field having been generated using the control information and having therein an N bit cyclic redundancy check (CRC) calculated using at least an N bit user equipment identity for the UE; and in which the UE further includes means for determining, via the user equipment circuitry, that the N bit CRC is correct using the N bit user equipment identity; and means for processing, via the user equipment circuitry, the control information upon the user equipment circuitry determining that the N bit CRC is correct. |
147 |
COMPUTATION CIRCUIT, ENCODING CIRCUIT, AND DECODING CIRCUIT |
US15341249 |
2016-11-02 |
US20170077951A1 |
2017-03-16 |
Yoshinori TOMITA |
Memories retain data blocks on which exclusive logical OR computation is performed, and selection circuits receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plurality of data blocks read from the memories on the basis of the selection signal, and XOR circuits (exclusive logical OR computation circuits) perform exclusive logical OR computation based on the two or more data blocks selected by the selection circuits. |
148 |
Systems and methods for decoding with late reliability information |
US14197408 |
2014-03-05 |
US09369152B2 |
2016-06-14 |
Dung Viet Nguyen; Shashi Kiran Chilappagari; Phong Sy Nguyen |
Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time. |
149 |
Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios |
US14681801 |
2015-04-08 |
US09300328B1 |
2016-03-29 |
Nedeljko Varnica |
Systems and methods are provided for decoding data. A decoder includes a syndrome memory, a state memory, and decoding circuitry communicatively coupled to the syndrome memory and the state memory. The decoding circuitry retrieves data related to a symbol from the syndrome memory. The decoding circuitry also retrieves data related to the symbol from the state memory. The decoding circuitry processes the data retrieved from the syndrome memory and the data retrieved from the state memory to determine whether to toggle a value of the symbol. The determination is based at least in part on whether the symbol of the data being decoded was previously toggled from an original state. |
150 |
Low complexity error correction using cyclic redundancy check (CRC) |
US13975433 |
2013-08-26 |
US09124298B2 |
2015-09-01 |
Robert W. Zopf |
Low complexity error correction using cyclic redundancy check (CRC). Communications between communication devices, sometimes including at least one redundant transmission from a transmitter to a receiver, undergo low complexity error correction. CRC may be employed in conjunction with using any desired type of ECC or using uncoded modulation. Based on CRC determined bit-errors, as few as a singular syndrome associated with a singular bit-error or a linear combination of syndromes associated with two or more singular bit-errors within two or more received signal sequences are employed to perform error correction of the received signal. Real time combinations of multiple syndromes associated with respective single bit-errors (that may themselves be calculated off-line) are employed in accordance with error correction. In addition to CRC, any ECC may be employed including convolutional code, RS code, turbo code, TCM code, TTCM code, LDPC code, or BCH code. |
151 |
Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios |
US13673371 |
2012-11-09 |
US09009578B1 |
2015-04-14 |
Nedeljko Varnica |
Systems and methods are provided for decoding data. A decoder includes a syndrome memory, a state memory, and decoding circuitry communicatively coupled to the syndrome memory and the state memory. The decoding circuitry retrieves data related to a symbol from the syndrome memory. The decoding circuitry also retrieves data related to the symbol from the state memory. The decoding circuitry processes the data retrieved from the syndrome memory and the data retrieved from the state memory to determine whether to toggle a value of the symbol. The determination is based at least in part on whether the symbol of the data being decoded was previously toggled from an original state. |
152 |
Apparatus and method for comparing pairs of binary words |
US13430147 |
2012-03-26 |
US08966355B2 |
2015-02-24 |
Thomas Kern; Ulrich Backhausen; Michael Goessel; Thomas Rabenalt |
An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted. |
153 |
Providing reliability metrics for decoding data in non-volatile storage |
US13888145 |
2013-05-06 |
US08966350B2 |
2015-02-24 |
Nima Mokhlesi; Henry Chin; Dengtao Zhao |
A set of reliability metrics is provided for use by an iterative probabilistic decoding process for non-volatile storage. A plurality of sense operations are performed on at least one set of non-volatile storage elements which are programmed to a plurality of programming states. A set of reliability metrics such as logarithmic likelihood ratios is provided based on the sense operations. The set of reliability metrics is can be used by an iterative probabilistic decoding process in determining a programming state of at least one non-volatile storage element based on at least one subsequent sense operation involving the at least one non-volatile storage element. The plurality of sense operations can be performed at different ages (e.g., number of program/erase cycles) of the at least one set of non-volatile storage elements and the set of reliability metrics can be based on an average over the different ages. |
154 |
Reduction of peak-to-average traffic ratio in distributed streaming systems |
US12579774 |
2009-10-15 |
US08938549B2 |
2015-01-20 |
Gal Zuckerman; Gil Thieberger |
Reduction of peak-to-average traffic ratio in distributed streaming systems, including a large number of fractional-storage CDN servers accessed via the Internet, and storing erasure-coded fragments encoded with a redundancy factor greater than one from streaming contents, and a very large number of assembling devices obtaining the fragments from the servers in order to reconstruct the streaming contents. The assembling devices are spread over different time zones spanning at least three hours and balance the bandwidth load between the servers. |
155 |
Fault tolerance in a distributed streaming system |
US12579662 |
2009-10-15 |
US08874774B2 |
2014-10-28 |
Gal Zuckerman; Gil Thieberger |
Fault tolerance in a distributed streaming system including fractional-storage CDN servers storing erasure-coded fragments encoded with a redundancy factor greater than one from segments of streaming contents. Each server delivers fragments, at a certain fragment delivery throughput, to multiple assembling devices using a fragment pull protocol, wherein a reduction in the fragment delivery throughput of one of the servers triggers a process in which at least some of the other servers approximately immediately increase their fragment delivery throughput as a reaction to the fragment pull protocol, to compensate for the reduced throughput. |
156 |
SYSTEMS AND METHODS FOR DECODING WITH LATE RELIABILITY INFORMATION |
US14197408 |
2014-03-05 |
US20140258809A1 |
2014-09-11 |
Dung Viet Nguyen; Shashi Kiran Chilappagari; Phong Sy Nguyen |
Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time. |
157 |
Peer-assisted fractional-storage streaming servers |
US12943782 |
2010-11-10 |
US08832295B2 |
2014-09-09 |
Gal Zuckerman; Gil Thieberger |
A system including a plurality of fractional-storage servers and a plurality of peer-to-peer devices. Substantially each of the servers and peer-to-peer devices stores less than a minimum amount of erasure-coded fragments needed to decode segments of streaming content. The system delivers at least the minimum amount of erasure-coded fragments needed to decode the segments of streaming content, from any group of the servers, or group of the servers plus peer-to-peer devices, that together store at least the minimum amount of erasure-coded fragments needed to decode the segments of streaming content. Optionally, the system supplements streaming capabilities of the servers during peak traffic periods by sending erasure-coded fragments stored on the peer-to-peer devices during the peak traffic periods. |
158 |
Random server selection for retrieving fragments under changing network conditions |
US12580166 |
2009-10-15 |
US08819260B2 |
2014-08-26 |
Gal Zuckerman; Gil Thieberger |
An assembling device obtaining enough erasure-coded fragments from fractional-storage CDN servers for reconstructing a first set of segments including at least one segment. The communication between the assembling device and the servers is subject to at least one type of communication fault, and the assembling device handles the communication faults by approximately randomly selecting on-the-fly servers from which to obtain additional fragments instead of fragments that failed to be obtained. |
159 |
METHOD AND APPARATUS FOR PROCESSING A DOWNLINK SHARED CHANNEL |
US14139037 |
2013-12-23 |
US20140185546A1 |
2014-07-03 |
Nader Bolourchi; Stephen E. Terry; Stephen G. Dick |
A method and apparatus is disclosed wherein a user equipment (UE) receives control information on a first channel and uses the control information to process a second channel. |
160 |
Method and apparatus for detecting free page and a method and apparatus for decoding error correction code using the method and apparatus for detecting free page |
US13859976 |
2013-04-10 |
US08738989B2 |
2014-05-27 |
Kwan-Ho Kim; Jong-In Kim; Young-Wook Jang; Hee-Dong Shin; Bong-Chun Kang; Jong-Jin Lee |
A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value. |