The range R of effective bits (those containing information) within the N bit outputs from an inner modem is determined and employed to select the M soft bits passed to a channel decoder, thereby avoiding underflow or overflow degrading the channel decoder performance. The average and standard deviation of IP values for a base-two logarithm of the N bit output are used to determine the range R of effective bits, with the N bits shifted and clipped based on the computed value of R so that the M most significant bits from that range R are passed to the channel decoder.

A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes. By evaluating many error-correcting codes according to the method, an optimal code according to selected criteria can be obtained.

L'invention permet la transmission de données avec encodage convolutif, où elle prévoit de réaliser, sur au moins une portion de données, des encodages indépendants séparés et rebouclés sur eux-mêmes. Ainsi, les données sont réparties sur un ou plusieurs cycles. Le groupement de plusieurs cycles en paquets permet une transmission discontinue lorsque nécessaire.

Le décodage pondéré est réalisé indépendamment cycle par cycle : l'invention prévoit de commencer à un lieu robuste (LR), de vraisemblance relativement élevée, et de terminer le décodage à un lieu faible (LF) de vraisemblance faible, en s'affranchissant de la notion de temps. Cela permet de limiter la taille des paquets d'erreurs lorsqu'ils surviennent et d'empêcher la propagation des paquets d'erreurs dû à un brouillage intentionnel ou non.

L'encodage et le décodage indépendants de données sont réalisables sans échanges de paramètres entre cycles et les paramètres de chaque cycle (taille ; redondance ; et longueur de contrainte) et peuvent être distincts. Ce traitement permet de spécifier différents degrés de protection et de retard en fonction de la nature des données à transmettre (voix ; données numériques ; signalisation etc..), d'autant que les cycles peuvent être courts : des performances identiques à celles obtenues dans le cas des codes convolutifs infinis sont obtenus à partir d'une soixantaine de bits pour le cas particulier du rendement ½ avec la longueur de contrainte 7.

Improper correction is avoided in decoding of an extended Reed-Solomon code. The decoding device includes: a syndrome computation section for computing input data syndromes from input data and corrected data syndromes from first corrected data obtained from the input data; an evaluator/locator polynomial deriving section for outputting coefficients at each order of an error evaluator polynomial and an error locator polynomial obtained based on the input data syndromes, as well as error magnitudes; a Chien search section for outputting roots of the error locator polynomial; and an error correction section for outputting data obtained by performing error correction for the input data when the input data has an error while otherwise outputting the input data, as the first corrected data, and also outputting the input data obtained by restoration when the first corrected data has an error while otherwise outputting the first corrected data, as second corrected data.

The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register (100) is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit (26) and a multiplexer (92). The value from the group and the predetermined value are compared in the arithmetic logic unit (26). A selector (88) is set to one of a first or second logic state. In the first logic state the selector (88) selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag (84) set by the comparison in the arithmetic logic unit (26) and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector (88) is set to a first state and the value is less than the predetermined value. The predetermined value is replaced with the extremum and the count register count is stored when the selector (88) is set to the second state and the value is greater than the predetermined value.

A switching circuit (8) switches operation states between a state in which m consecutive bit data of an M-sequence reception code having a period (2^m - 1), which is input to a measurement terminal (7), are set in a feedback shift register (FSR) (9), and a state in which the FSR (9) is set in a closed-loop state to be set in a self-running state. A synchronization detection comparator (10) sequentially compares each bit data output from the FSR (9) in a self-running state with corresponding bit data of the reception code. On the basis of the comparison result from the synchronization detection comparator (10), a control section (15) determines that the bit data output from the FSR (9) are a reference code, or outputs a command to the FSR (9) through the switching circuit (8) to fetch the m bit data again. A storage circuit (18) stores consecutive bit data of the reception code which are input before the control section determines that the bit data are the reference code, and outputs the stored bit data upon delaying them by a predetermined period of time. A bit error detection comparator (19) sequentially compares the bit data of the delayed reception code output from the storage circuit (18) with the bit data output from the FSR (9) and determined as the reference code.

An error correcting scheme for processing data which is transmitted on a broadcast and/or CATV network and utilizes the IEEE 802.4 three-level duobinary AM/PSK (phase shift keying) coding format. The error correcting scheme utilizes two thresholders. One of the thresholders makes data (1 or 0) decisions while the other thresholder makes non-data or no non-data (non-data) decisions. Pattern matching and windowing are used to detect non-data symbols which are corrected if the non-data symbols deviate from a predetermined pattern. The template used in the pattern matching is determined from the state of a demodulator.

The present disclosure presents symbol mapping for any desired error correction code (ECC) and/or uncoded modulation. A cross-shaped constellation is employed to perform symbol mapping. The cross-shaped constellation is generated from a rectangle-shaped constellation. Considering the rectangle-shaped constellation and its left hand side, a first constellation point subset located along that left hand side are moved to be along a top of the cross-shaped constellation while a second constellation point subset located along that left hand side are moved to be along a bottom of the cross-shaped constellation. For example, considering an embodiment having four constellation point subsets along the left hand side of the rectangle-shaped constellation, two of those subsets are moved to be along the top of the cross-shaped constellation while two other subsets of the constellation points along the left hand side are moved to be along the bottom of the cross-shaped constellation.

The present disclosure presents symbol mapping for any desired error correction code (ECC) and/or uncoded modulation. A cross-shaped constellation is employed to perform symbol mapping. The cross-shaped constellation is generated from a rectangle-shaped constellation. Considering the rectangle-shaped constellation and its left hand side, a first constellation point subset located along that left hand side are moved to be along a top of the cross-shaped constellation while a second constellation point subset located along that left hand side are moved to be along a bottom of the cross-shaped constellation. For example, considering an embodiment having four constellation point subsets along the left hand side of the rectangle-shaped constellation, two of those subsets are moved to be along the top of the cross-shaped constellation while two other subsets of the constellation points along the left hand side are moved to be along the bottom of the cross-shaped constellation.