| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 201 | Decoding and error correction method | US10858866 | 2004-06-02 | US20050010851A1 | 2005-01-13 | Hubert Degoirat; Loic Parlier |
| A decoding and error correcting method is applicable to a secured code word that may have an error relative to an initial secured code word. The method includes an error correcting step, and a decoding step using a decoding function. The decoding step may be carried out before the error correcting step, and includes applying the decoding function to the secured code word to obtain a secured decoded word containing a coded error. The method reduces the decoding and error correcting time of the secured code word. | ||||||
| 202 | Convolutional coding and decoding method and system | US10259567 | 2002-09-30 | US20040216029A1 | 2004-10-28 | Thibault Gallet; Andre Marguinaud; Brigitte Romann |
| A method is disclosed of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. Thus the data is distributed over one or more cycles. A plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors when errors occur and prevents the propagation of packets of errors due to intentional or non-intentional scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. This processing also specifies different degrees of protection and time-delay as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.), especially as the cycles can be short: performance identical to that obtained in the case of infinite convolutional codes is obtained from around 60 bits for the particular case of a redundancy of null and a constraint length of 7. | ||||||
| 203 | Method and apparatus for turbo decoding of trellis coded modulated signal transmissions | US09410220 | 1999-09-30 | US06795507B1 | 2004-09-21 | Weizhuang Xin; Ning Kong |
| An implementation of an iterative decoding system within a Trellis Coded Modulation communications environment. In a disclosed embodiment of the present invention, a communication system is described wherein the transmitter uses a channel encoder (consisting of either a convolutional encoder or a block encoder) as an outer encoder. The channel encoded signal is then passed through an interleaver and provided to a Trellis Coded Modulation encoder which acts as an inner encoder. The encoded signal may then be transmitted over the channel. On the decoding side, the disclosed embodiment of the present invention advantageously applies iterative decoding steps to decode the received Trellis Coded Modulated signals, resulting in improved coding gains and a decrease in BER as compared with a conventional non-iterative approach. | ||||||
| 204 | Receiver with improved decoder | US09738645 | 2000-12-15 | US06732324B2 | 2004-05-04 | Arie Geert Cornelis Koppelaar |
| A receiver for receiving digital signals comprises a front end (18) for receiving RF signals and converting them into an input signal for an de-interleaver 22 for obtaining a de-interleaved signal. The output of the de-interleaver is connected to a decoder (24) which can be a Reed-Solomon decoder. The decoder (24) is able to use erasure information which indicates possible positions of errors in the de-interleaved signal for increasing the number of errors the decoder (24) can correct. In order to improve the error correcting capabilities of the receiver, this receiver comprises error prediction means (26) which predict the position of errors in the next codewords due to error bursts from the errors found in the present codeword. Such a predicted error is handled as an erasure by the decoder (24). To prevent that more erasures are presented to the decoder (24) than it can handle, it is proposed according to the present invention to determine a probability measure for all predicted errors and to present only those errors to the decoder (24) having the largest probability. | ||||||
| 205 | BER calculation device for a decoder | US10259303 | 2002-09-30 | US20040064778A1 | 2004-04-01 | Benjamin John Widdup |
| In a decoder, the BER is calculated during a decode operation of the decoder. Access to decoder components for obtaining signal data for use in calculating the BER is provided during the decode operation when the components are not used by the decoder. An HDA early termination signal is used to confirm an accurate BER calculation. | ||||||
| 206 | Apparatus for iterative hard-decision forward error correction decoding | US10113488 | 2002-04-01 | US20030188248A1 | 2003-10-02 | Michael Kauschke; Carsten Poppinga |
| A apparatus for iterative hard-decision forward error correction decoding is described. A method comprises a binary receiver to convert an optical signal to an electrical signal, the electrical signal having a set of information symbols and a set of redundancy symbols, the set of redundancy symbols generated by different forward error correction (FEC) encoding schemes, and a first of a plurality of decoders coupled with the binary receiver and the plurality of decoders coupled together, each of the plurality of decoders to decode the set of information symbols with the set of redundancy symbols in accordance with the different FEC encoding schemes. | ||||||
| 207 | Method for mathematically processing two quantities in an electronic circuit | US09628578 | 2000-07-31 | US06584486B1 | 2003-06-24 | Markus Helfenstein; Hans-Andrea Loeliger; Felix Lustenberger; Felix Tarköy |
| The method serves to add at least two values by means of a circuit. Both input values and output values are represented in differential form, either as a pair of voltages or as a pair of currents. The circuit consists of four transistors; it has a pair of current inputs for one of the input values, a pair of voltage inputs for the other input value, and a pair of current outputs for the output value. The voltage between the two voltage inputs corresponds to the first input value; the quotient of the currents through the two current inputs corresponds to the exponential of the other input value; and the quotient of the currents through the two current outputs corresponds to the exponential of the sum of the two input values. Values represented by voltages are easily transformed into current representation, and vice versa. The method is suitable for a variety of applications and the circuit can be cascaded both with copies of itself and with other circuits. | ||||||
| 208 | Enhanced coding for informed decoders | US10219418 | 2002-08-15 | US20030095056A1 | 2003-05-22 | Ludovicus Marinus Gerardus Maria Tolhuizen; Martinus Wilhelmus Blum; Constant Paul Marie Jozef Baggen |
| The invention relates to method of encoding address words (a) comprising address symbols (a0, a1, . . . , aknull1) into codewords (c) of a code (C) for providing an enhanced error correction capability if at least one information symbol (m1) of information words (m) is known a priori to a decoder decoding received, possibly mutilated codewords (r). The invention relates further to a method of decoding possibly mutilated codewords (r). In order to design a code of which the correction power is enhanced if some information symbols are known to the decoder prior to decoding it is proposed according to the invention that the address words (a) are encoded into information words (m) such that that address words comprising addresses being close to each other share a plurality of information symbols and that said information words (m) are encoded into codewords (c) using a generator matrix (G) which is selected such that the minimum Hamming distance of at least one subcode (Cnull) of said code (C) is larger than the minimum Hamming distance of said code (C) and that a subcode generator matrix (Gnull) of said subcode (Cnull) derives from said generator matrix (G) of said code (C) by omitting the at least one row from said generator matrix (G) corresponding to said at least one a priori known information symbol (m1). | ||||||
| 209 | Combinational circuit, and encoder, decoder and semiconductor device using this combinational circuit | US10091774 | 2002-03-06 | US20030063554A1 | 2003-04-03 | Sumio Morioka; Yasunao Katayama; Toshiyuki Yamane |
| A combinational circuit comprises: a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2m) (m is an integer equal to or greater than 2), wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, according to the present invention, these multipliers each include an adder connected between an AND calculator and an output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common. | ||||||
| 210 | Evaluating and optimizing error-correcting codes using a renormalization group transformation | US09858358 | 2001-05-16 | US20030014717A1 | 2003-01-16 | Jonathan S. Yedidia; Jean-Philippe M. Bouchaud |
| A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes. By evaluating many error-correcting codes according to the method, an optimal code according to selected criteria can be obtained. | ||||||
| 211 | Method for adapting the data blocks to be supplied to a turbo coder and corresponding communications apparatus | US10204608 | 2002-08-22 | US20030014715A1 | 2003-01-16 | Andreas Lobinger; Bernhard Raaf; Ralf Wiedmann |
| A transmitting device in a mobile communication system is disclosed. In the transmitting device, an encoder receives an information bit stream in a frame, which is as long as an integer multiple of a predetermined value, and generates an information symbol, a first panty symbol, and a second parity symbol by encoding each information bit. An interleaver sequentially arranges the information symbols and the first and second parity symbols by rows in an array with an integer number of rows and an integer number of columns. The interleaver reorders the columns in the array according to a predetermined rule. The interleaver further outputs a plurality of radio frames in a stream, by reading the symbols by going down each column, starting at the leftmost column and proceeding right. Each radio frame has a predetermined size. A demultiplexer demultiplexes each of the radio frames received from the interleaver into a stream of information symbols, a stream of first parity symbols, and a stream of second parity symbols. A rate matcher bypasses the stream of information symbols and punctures the streams of the first and second parity symbols for rate matching. | ||||||
| 212 | Method and apparatus to perform customized error handling | US09815441 | 2001-03-22 | US20020184589A1 | 2002-12-05 | David Arthur Eatough; James Sferas |
| A method and apparatus to perform customized error handling is described. | ||||||
| 213 | Method of and apparatus for decoding and processing messages | US866562 | 1997-05-30 | US5867510A | 1999-02-02 | Scott A. Steele |
| A mobile station (104) processes a paging message having information data mapped to a cyclical redundancy check (CRC) error detection code and divided into a plurality of CAC data portions mapped to a plurality of Bose-Chaudhuri-Hocquenghem (BCH) error correction codes. A BCH forward error corrector (FEC) (150) generates a plurality of BCH syndromes (538) to correct single errors that may exist in each of the plurality of CAC data portions (402), and thereby generates a plurality of post-correction CAC data portions (504). A cyclical redundancy check (CRC) error detector (152) detects if an error exists in the plurality of post-correction CAC data portions (504). An error detector (174) detects if BCH syndromes (552-562) corresponding to post-correction CAC data portions (518-528) have values of zero. When the CRC error detector (152) detects an error and the error detector (174) detects that BCH syndromes (552-562) have values of zero, the mobile station (104) processes the paging message and performs a page response function in response to detecting a page. | ||||||
| 214 | Method and apparatus for a high speed cyclical redundancy check system | US474397 | 1995-06-07 | US5854800A | 1998-12-29 | Mark Thomann; Huy Thanh Vo; Charles L. Ingalls |
| A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle. | ||||||
| 215 | Enhanced decoding of interleaved error correcting codes | US792113 | 1991-11-14 | US5299208A | 1994-03-29 | Miguel M. Blaum; Henricus C. Van Tilborg |
| Decoding power is enhanced by (1) flagging only those codewords where the ECC capability has been exceeded; (2) permitting codewords to be of any byte length (n) and codeword depth (.lambda.) subject only to the requirement that n and .lambda. be relatively prime; and (3) interleaving encoded bytes of successive codewords diagonally in a single continuous sequence to form an array with a toroidal topology so that all burst errors will be continuous from codeword to codeword, irrespective of where they occur in the array. These attributes assure that there will never be a problem with burst errors affecting.ltoreq..lambda. rows because there is no "last row" and "first row". | ||||||
| 216 | Probabilistic fade forecasting | US141241 | 1988-01-06 | US4835772A | 1989-05-30 | Robert E. Peile; Earl T. Cohen |
| A block of helically interleaved codewords is received in a de-interleaving array. A succession of codewords obtained from the de-interleaving array are decoded in a process in which each error pattern in a given codeword position provides a prediction of the presence or absence of an erasure in the adjacent codeword position of the next codeword. This prediction is obtained by addressing a look-up table with the error pattern. In one embodiment of the invention, the erasure prediction is computed recursively from previous erasure predictions using individual skepticism factors and forgetting factors for each codeword symbol position. | ||||||
| 217 | Error correction scheme | US741400 | 1985-06-05 | US4677627A | 1987-06-30 | Ju-Hi J. Hong |
| An error correcting scheme for processing data which is transmitted on a broadband and/or CATV network and utilizes the IEEE 802.4 three-level duobinary AM/PSK (phase shift keying) coding format. The error correcting scheme utilizes two thresholders. One of the thresholders makes data (1 or 0) decisions while the other thresholder makes non-data or no non-data (non-data) decisions. Pattern matching and windowing are used to detect non-data symbols which are corrected if the non-data symbols deviate from a predetermined pattern. The template used in the pattern matching is determined from the state of a demodulator. | ||||||
| 218 | Interleavers for digital communications | US518213 | 1983-07-28 | US4559625A | 1985-12-17 | Elwyn R. Berlekamp; Po Tong |
| An improved method and apparatus for interleaving block codes exploits helical symmetry whereby correspondingly positioned code symbols of code words of length n interleaved to depth i, i<n, are separated on the channel by .alpha.i+.beta. symbol intervals where 1+.gamma..gtoreq.i is averaged over the i correspondingly positioned symbols and .alpha.and .vertline..beta..vertline. are integers >1. The requirement for synchrony is reduced to a period counted modulo n instead of mod (n.times.i). For the case i=n-1, the total interleaving delay is reduced to 2(n-1)n and phase dependence of burst error onset is minimized. The performance of the de-interleaver is enhanced through a pseudo fade detector implemented by creating erasures prior to decoding, at certain positions for codewords subsequent to confirmed error. Synchronization of interleaver and de-interleaver is accomplished in apparatus which inspects all c contiguous bit patterns corresponding to a c bit synch symbol. To each c contiguous bit pattern of the data stream there is associated a probability counter for incrementing when the synch pattern is detected and decremented otherwise. Maximum probability establishes synch. | ||||||
| 219 | レート判定装置、レート判定方法及び受信装置 | JP2016241909 | 2016-12-14 | JP2018098662A | 2018-06-21 | 金 基重; 岡田 博之; 松井 直大; 廣田 智章 |
| 【課題】データ通信中にビットレートを判定することができる。 【解決手段】レート判定装置1は、FSK変調方式で変調された伝送フレームを受信する受信部2と、受信した伝送フレームにおけるプリアンブル部の周期に基づいて、シンボルレートを検出するシンボルレート検出部3と、受信した伝送フレームの周波数偏移に基づいて、多値変調された多値シンボルを検出する多値シンボル検出部4と、検出したシンボルレート及び前記検出した多値シンボルに基づいて、ビットレートを判定するビットレート判定部5と、を備える、 【選択図】図2 |
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| 220 | 端末、パケット復号方法、および、プログラムが記憶された記憶媒体 | JP2016520938 | 2015-05-19 | JPWO2015178018A1 | 2017-04-20 | 佑樹 林; 鈴木 順; 順 鈴木; 真樹 菅 |
| [課題]レートレス符号化に基づく符号化パケットからソースパケットを復号化する処理を高速化すること。[解決手段]端末は、n行n列の行列とnビットのフラグを保持する記憶手段と、受信したnビットの符号化パケットと前記フラグの双方において1となる要素を抽出し、抽出した要素の要素番号に相当する前記行列の行ベクトルを受信した符号化パケットに対して排他的論理和演算する処理を、抽出したすべての要素について行い、前記排他的論理和演算後の符号化パケットにおいて最初に1となる要素を判定し、判定した要素の要素番号に相当する行ベクトルとして、前記排他的論理和演算後の符号化パケットを前記行列に挿入する計算手段と、を備えている。 | ||||||
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