Methods and systems are disclosed for decoding digital data received by a correspondent device (154) over a communication channel (156). The data includes a component corresponding to a plurality of values unknown to the correspondent device (154) and a component corresponding to one or more values known a priori by the correspondent device (154). To perform decoding, the correspondent device (154) retrieves from memory (162) at least one of the one or more known values. The correspondent device (154) then applies a statistical measure using the known value(s) to estimate the location of the component corresponding to the one or more known values. The one or more known values and the estimated location of the component corresponding to the one or more known values are then used by a decoder (160) to assist in decoding the data.

A user equipment (UE) comprising means for receiving a first wireless signal of a control channel, wherein the first wireless signal comprises an N bit field and control information and the N bit field comprises an N bit cyclic redundancy check (CRC) modulo two added to an N bit UE identity; means for determining whether criteria is met wherein the criteria includes the CRC is correct and the UE identity is any one of a plurality of UE identities associated with the UE; and means for using the control information to process a downlink shared channel on a condition that the criteria is met,

An iterative decoder for use in a WLAN includes an inner decoder/detector, a first subtraction module, a deinterleaving module, an outer decoder, a second subtraction module, an interleaving module, and a determining module. The inner decoder/detector determines inner coded bits and extrinsic information of the inner coded bits from symbol vector based on a channel matrix and inner extrinsic information feedback. The first subtraction module subtracts the inner extrinsic information feedback from the extrinsic information of the inner coded bits. The deinterleaving module deinterleaves the output of the first subtraction module to produce deinterleaved inner extrinsic information. The outer decoder determines outer coded bits and extrinsic information of the outer coded bits from the deinterleaved inner extrinsic information. The second subtraction module subtracts the deinterleaved inner extrinsic information from the extrinsic information of the outer coded bits. The interleaving module interleaves the output of the second subtraction module to produce the inner extrinsic information feedback. The determining module produces decoded bits based on the outer coded bits.

A coding section 101 turbo-codes transmit data and outputs parity bit data, and systematic bit data for which good quality is required. A modulation section 102 modulates the parity bit data and systematic bit data. A subcarrier allocation section 103 rearranges the transmit data so that systematic bit data is allocated to subcarriers in the vicinity of the center frequency and parity bit data is allocated to subcarriers in the vicinity of both ends. An OFDM section 104 performs orthogonal frequency division multiplexing of the transmit data, and allocates parity bit data and systematic bit data to respective subcarriers. By this means, it is possible to improve significantly the error rate characteristics of transmit data for which good quality is required, and prevent degradation of the quality of transmit data for which good quality is required.

The present invention achieves technical advantages as a multiplier circuit. The multiplier circuit multiplies GF (2¹³) vectors to implement sigma calculations and a Chien search. This multiplier takes two inputs to be multiplied and outputs the resulting multiplication in GF (2¹³) vectors in only one clock cycle. The multiplier circuit is customized to operate with OC-48 and OC-192 data, and is operable to meet the SONET Standard T1X1.5/99-218R3 and the SDH Standard ITU-T.G.707/Y.1322.

A method and apparatus for reducing the average number of iterations in an iterative decoding technique includes the step of at the end of each decoding iteration or sub-iteration estimating the transmitted bit sequence by processing the available information. A signature for the estimation is then generated of reach iteration or sub-iteration. If this signature is the first signature generated, the decoder proceeds to the next process. When there exists a signature generated for the previous decoding iteration or sub-iteration step, the new signature for the current iteration is compared with the signature (old signature) for this previous iteration. If the two signatures match, the decoding iteration stops. Otherwise, the decoding iteration process continues.

The present invention achieves technical advantages as a sigma calculation circuit for in-band FEC decoding. The present invention includes discrete mathematics units using parallel structure to accomplish the computation with low latency. A custom multiplier and squarer are utilized to do the multiplications, squaring, and cubing. Addition is done using XOR GATES. The sigma calculation circuit is customized to operate with OC-48 and OC-192 data, and is operable to meet both the SONET Standard T1X1.5/99-218R3 and the SDH Standard.

In accordance with the invention, a method of generating a soft symbol confidence level for use in decoding a received digital signal includes calculating a difference between two potential next state accumulated costs (PNS₀₀, PNS₀₁) to provide a soft symbol confidence level. Simultaneously with calculating the difference between two potential next state accumulated costs, performing a compare-select operation to identify one of the two potential next state accumulated costs as an extremum of the two present state accumulated costs. The invention also teaches a circuit for generating a soft symbol confidence level such as in a decoder. The circuit includes first and second adders for receiving first and second potential next state accumulated costs. Simultaneously the potential next state accumulated costs are compared in one of the adders while the difference is taken in the other adder as a soft symbol confidence level. A selector selects one of the first and second potential next state accumulated costs as an extremum based on a flag set by one of the adders. The circuit may also provide a register in which to store one or more traceback bits, and a shift register for packing multiple traceback bits into a register or word.