| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 241 | Decoding method and program, and decoder circuit using the same | JP2002361586 | 2002-12-13 | JP2004194128A | 2004-07-08 | SEKI KATSUTOSHI |
| PROBLEM TO BE SOLVED: To provide a decoding method capable of significantly reducing an amount of calculation. SOLUTION: A first stage inner code decoder 11 corrects an inner code (step S1), a first stage outer code decoder 12 corrects an outer code and further creates an update flag UDI for indicating whether the inner code is updated according to the correction and outputs it (step S2). A second stage inner decoder 13 refers to the update flag UDI to skip the inner code correction processing where the number of errors has not been reduced in the correction in step S2 (third step). COPYRIGHT: (C)2004,JPO&NCIPI | ||||||
| 242 | Multi-carrier transmission apparatus and multi-carrier transmission method | JP2003007616 | 2003-01-15 | JP2004187257A | 2004-07-02 | SUDO HIROAKI |
| <P>PROBLEM TO BE SOLVED: To remarkably improve an error rate characteristic of transmission data for which excellent quality is required, and to prevent deterioration in the quality of the transmission data for which excellent quality is required. <P>SOLUTION: An encoding part 101 performs turbo encoding to the transmission data to output parity bit data and systematic bit data for which high quality is required. A modulation part 102 modulates the parity bit data and the systematic bit data. A subcarrier location part 103 relocates the transmission data, such that the systematic bit data is located in a subcarrier near a center frequency and the parity bit data are located in a subcarrier near both ends. An OFDM part 104 performs orthogonal frequency division multiplexing on the transmission data to locate the parity bit data and the systematic bit data in the subcarriers. <P>COPYRIGHT: (C)2004,JPO&NCIPI | ||||||
| 243 | Receiver with an improved decoder | JP2001547747 | 2000-12-05 | JP2003518800A | 2003-06-10 | へー セー コッぺラール，アリー |
| (57)【要約】 デジタル信号を受信する受信機は、ＲＦ信号を受信し、デインターリーブされた信号のためにそれらをデインターリーバー２２に対する入力信号に変換するフロンドエンドを含む。 デインターリーバーの出力はリードソロモンデコーダーに接続される。 デコーダーは、訂正できるエラーの数を増加するためデインターリーブ信号内の考えられるエラー位置を特定する消失情報を使用できる。 受信機のエラー訂正能力を改善すべく、受信機は、現在のコードワード内で発見されたエラーからのエラーバーストに起因した次のコードワード内のエラー位置を予測するエラープレディクターを含む。 予測エラー位置は、デコーダーによって消失として処理される。 デコーダーが処理できるよりも多くの消失がデコーダーに付与されるのを防止するため、全ての予測エラーに対して可能性の指標を決定し、最も大きな確率を有するエラーだけがデコーダーに与えられることが提案される。 | ||||||
| 244 | Combinational circuit, encoder by using combinational circuit, decoder, and semiconductor device | JP2001196027 | 2001-06-28 | JP2002335165A | 2002-11-22 | MORIOKA SUMIO; KATAYAMA YASUNAO; YAMANE TOSHIYUKI |
| PROBLEM TO BE SOLVED: To provide a combinational circuit, an encoder by using the combinational circuit, a decoder, and a semiconductor device. SOLUTION: The combinational circuit includes a plurality of multipliers, for multiplying individually two or more encoded digital signals in a Galois field GF (2<m> ), where (m) is an integer of 2 or larger. The multiplier is composed of an input-side XOR processor, an AND processor and an output-side XOR processor, and the input-side XOR processor functions in common, for the plurality of multipliers. The multiplier includes an adder connected between the AND processor and the output-side XOR processor, and the output-side XOR processor is used in common. The output from the AND processors of the multipliers are added by the adder, and the added result can be processed by the common output-side XOR processor. | ||||||
| 245 | Multi-rate serial Viterbi decoder for the code division multiple access system applied | JP50994995 | 1994-09-23 | JP3290989B2 | 2002-06-10 | ウルフ、ジャック・キール; キンドレッド、ダニエル・レイ; ゼハビ、エフレイム; バトラー、ブライアン・ケー |
| 246 | Coding support device, decoding support device, radio transmitter and radio receiver | JP21529099 | 1999-07-29 | JP2001044854A | 2001-02-16 | FUJII MASASATO |
| PROBLEM TO BE SOLVED: To realize coding and decoding with high speed and high accuracy, without significantly revising basic configuration of hardware and software. SOLUTION: This coding support device is configured with an arithmetic object storage means 11, that sequentially stores words in a plurality of bits and received being divided into certain word lengths, an argument storage means 12 that stores an argument to be applicable to an arithmetic operation of a word stored in the arithmetic object storage means 11 and the word stored continuously in the arithmetic object storage means 11, as a result of the arithmetic operation precedingly applied to the word, and an arithmetic means 13 that apply coding defined as an arithmetic operation to a combination of logical values of respective bits of the word stored in the arithmetic object storage means 11 and of the argument stored in the argument storage means 12. | ||||||
| 247 | Fast cyclic redundancy check system that uses a programmable architecture | JP50041797 | 1995-12-08 | JP3020009B2 | 2000-03-15 | インガルス、チャールズ・エル; ヴォー、フイ・タン; トーマン、マーク・アール |
| A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle. | ||||||
| 248 | Generation method for confidence level of soft symbol | JP33315398 | 1998-11-24 | JPH11330988A | 1999-11-30 | SIMANAPALLI SIVANAND; TAT LARRY R |
| PROBLEM TO BE SOLVED: To generate a soft symbol which is used when the received digital signals are decoded by deciding the difference between the accumulation costs of the next states having the 1st and 2nd possibilities and also performing the comparison and selection operations to specify one of both accumulation costs as the extreme value of the 1st and 2nd next states. SOLUTION: A data arithmetic unit 20 performs the calculation of a pipeline system to decide the difference between the accumulation costs PNS 00 and PNS 01 of the next states having the 1st and 2nd possibilities. The unit 20 also simultaneously gives the PNS 00 and PNS 01 to the adders 26 and 30 respectively. The adder 26 compares the PNS 00 with PNS 01 and the adder 30 defines the difference between them as a soft shift confidence level. Then the unit 20 selects the PNS 00 or PNS 01 as the maximum or minimum value based on the flag that is set via the comparison of the adder 26 and also stores one or more trace back bits in a register. Thus, it is possible to generate the soft symbol confidence level that is used for decoding the received digital signals. COPYRIGHT: (C)1999,JPO | ||||||
| 249 | Fast cyclic redundancy check system that uses a programmable architecture | JP50041797 | 1995-12-08 | JPH10510411A | 1998-10-06 | インガルス、チャールズ・エル; ヴォー、フイ・タン; トーマン、マーク・アール |
| A high speed cyclical redundancy check system for use in digital systems. The high speed cyclical redundancy check system providing programmable error correction functions for different data protocols. The high speed cyclical redundancy check system providing programmable data paths for minimizing overhead and maximizing throughput. The system supporting multiple operations in a single cycle. | ||||||
| 250 | RFID receiver and method of extracting data bits encoded in a radio signal | US15615973 | 2017-06-07 | US10152619B2 | 2018-12-11 | Thomas Knoblauch |
| An RFID receiver (1) comprises an antenna (11) configured to receive a radio signal (20) from an RFID transmitter (2) and to generate an electrical signal (110) from the radio signal (20) received from the RFID transmitter (2). A decoder circuit (10) is connected to the antenna (11) and configured to extract from the electrical signal (110) generated by the antenna (11) data bits encoded in the electrical signal (110). The decoder circuit (10) comprises an analog-to-digital converter (12) connected directly to the antenna (11) and configured to generate a digital input signal (13) from the electrical signal (110) generated by the antenna (11). A bit extractor (14) is connected to the analog-to-digital converter (12) and configured to extract the data bits from the digital input (13) signal generated by the analog-to-digital converter (12). | ||||||
| 251 | BCH decorder in which folded multiplier is equipped | US15221083 | 2016-07-27 | US10009041B2 | 2018-06-26 | Jongsun Park; Hoyoung Tang |
| Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage. | ||||||
| 252 | RFID RECEIVER AND METHOD OF EXTRACTING DATA BITS ENCODED IN A RADIO SIGNAL | US15615973 | 2017-06-07 | US20170372102A1 | 2017-12-28 | Thomas KNOBLAUCH |
| An RFID receiver (1) comprises an antenna (11) configured to receive a radio signal (20) from an RFID transmitter (2) and to generate an electrical signal (110) from the radio signal (20) received from the RFID transmitter (2). A decoder circuit (10) is connected to the antenna (11) and configured to extract from the electrical signal (110) generated by the antenna (11) data bits encoded in the electrical signal (110). The decoder circuit (10) comprises an analog-to-digital converter (12) connected directly to the antenna (11) and configured to generate a digital input signal (13) from the electrical signal (110) generated by the antenna (11). A bit extractor (14) is connected to the analog-to-digital converter (12) and configured to extract the data bits from the digital input (13) signal generated by the analog-to-digital converter (12). | ||||||
| 253 | Pipelined decoder with syndrome feedback path | US14924249 | 2015-10-27 | US09785502B2 | 2017-10-10 | Ran Zamir; Omer Fainzilber; Eran Sharon |
| A device includes a memory a memory configured to store syndromes. The device also includes a pipelined data processing unit and routing circuitry. The routing circuitry includes a first input coupled to the memory and includes a second input coupled to an output of the pipelined data processing unit. | ||||||
| 254 | BCH DECORDER IN WHICH FOLDED MULTIPLIER IS EQUIPPED | US15221083 | 2016-07-27 | US20170288700A1 | 2017-10-05 | Jongsun Park; Hoyoung Tang |
| Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage. | ||||||
| 255 | Managing integrity of framed payloads using redundant signals | US14948203 | 2015-11-20 | US09680606B2 | 2017-06-13 | Sergio Licardie; Rishipal Arya; Robert Brown |
| A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network. | ||||||
| 256 | TERMINAL, PACKET DECODING METHOD, AND STORAGE MEDIUM IN WHICH PROGRAM IS STORED | US15312808 | 2015-05-19 | US20170155408A1 | 2017-06-01 | Yuki HAYASHI; Jun SUZUKI; Masaki KAN |
| To speed up processing for decoding a source packet from a coded packet based on rateless coding, a terminal is provided with: a storage unit which holds a matrix with n rows and n columns and an n-bit flag; and a calculation unit which performs processing for extracting an element that becomes 1 in both a received n-bit coded packet and the flag, and performing processing for performing an exclusive OR operation of a row vector of the matrix that corresponds to the element number of the extracted element and the received coded packet on all extracted elements, determines an element that is the first to become 1 in the coded packet after the exclusive OR operation, and inserts, into the matrix, the coded packet after the exclusive OR operation as a row vector corresponding to the element number of the determined element. | ||||||
| 257 | PIPELINED DECODER WITH SYNDROME FEEDBACK PATH | US14924249 | 2015-10-27 | US20170116077A1 | 2017-04-27 | Ran Zamir; Omer Fainzilber; Eran Sharon |
| A device includes a memory a memory configured to store syndromes. The device also includes a pipelined data processing unit and routing circuitry. The routing circuitry includes a first input coupled to the memory and includes a second input coupled to an output of the pipelined data processing unit. | ||||||
| 258 | CIRCUIT DESIGN SUPPORT METHOD, CIRCUIT DESIGN SUPPORT APPARATUS, AND RECORDING MEDIUM | US15254375 | 2016-09-01 | US20160371414A1 | 2016-12-22 | Yoshinori Tomita |
| A circuit design support apparatus acquires an encoding matrix and information indicative of a start timing. For each timing after the start timing indicated by the acquired information, among the timings corresponding to column vectors of the encoding matrix, the circuit design support apparatus identifies among first partial data stored in BRAMs, a first partial data overwritten by a second partial data at the timing. For each of the timings after the start timing, the circuit design support apparatus identifies an XOR operation based on the identified first partial data among multiple XOR operations. For each of the timings after the start timing, the circuit design support apparatus identifies among timings before the start timing included in the timings, a timing having the same operation result of the identified XOR operation as the operation result of the identified XOR operation based on the vector corresponding to the timing. | ||||||
| 259 | Computing device storing look-up tables for computation of a function | US14396971 | 2013-10-21 | US09525435B2 | 2016-12-20 | Paulus Mathias Hubertus Mechtildis Antonius Gorissen; Ludovicus Marinus Gerardus Maria Tolhuizen |
| A computing device is configured to compute a function of one or more inputs, comprising look-up tables mapping input values to output values, wherein the inputs values have a bit size equal to a first code word bit size of a first error correcting code, such that any two input values that each differ at most by a first error threshold of bits with a same code word of the first error correcting code are mapped to respective output values that each differ at most by a second error threshold number of bits with a same code word of a second error correcting. | ||||||
| 260 | Reconstructing data stored across archival data storage devices | US14276676 | 2014-05-13 | US09430321B2 | 2016-08-30 | David Slik |
| Techniques for operating a storage system are disclosed. A read request with an object identifier for a data object is received. A synchronous group of data storage devices across a plurality of enclosures is identified. The synchronous group is associated with the object identifier. A request is sent to the plurality of enclosures to synchronously activate the data storage devices in the synchronous group. After sending the request, data fragments associated with the object identifier are retrieved from the synchronous group of data storage devices. The data fragments are erasure decoded into a contiguous data range to reconstruct the data object. | ||||||
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