| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | Method and device for data transmission for cdma | JP36274097 | 1997-12-12 | JPH11177527A | 1999-07-02 | AIZAWA JUNICHI; KATO OSAMU; KAMI TOYOKI |
| PROBLEM TO BE SOLVED: To make the scale of hardware of a decoder small by improving transmission quality, decreasing a processing quantity at decoding time and to reduce the memory capacity. SOLUTION: A known bit insert section 502 at a transmitter side inserts known bits with a predetermined length at a predetermined position between data, a termination bit insert section 503 inserts a termination bit, the data are assembled into frames. A frame length detection section 504 detects the length of the frame data, a convolution coding section 505 encodes the data. When the frame data have a prescribed length as a result of detection, the code data are sent. Then increase in redundancy to add a dummy bit without information is avoided and the transmission quality is enhanced and the memory capacity is reduced by reducing the processing quantity at decoding by the receiver side thereby making the scale of the hardware of the decoder small. | ||||||
| 162 | Device and method for detecting and correcting error | JP29655896 | 1996-11-08 | JPH09214359A | 1997-08-15 | PIREE FUIRIPE; KUDOREE PASUKARU |
| PROBLEM TO BE SOLVED: To enable the detection and correction of error during transmission by forming a full transmission sequence by adding two coherence numbers to an initial sequence, and deciding it so as to become a specified modulo P value. SOLUTION: A device 10 is composed of a CPU 11, RAM 12, ROM 13, input port 14, output port 15 and modulator 17 through an address/data bus 16. For coherence numbers RO and RI to be stored in the RAM12 two pieces of specified coherence check combination are applied to the full transmission sequence and they are selected so that a modulo 67 for respective results can give a specified value. The CPU 11 performs encoding, starts a transmission phase later, performs decoding in a reception phase and retrieves a transmission error by applying the combination. By applying the combination to the received number in the full sequence, the transmission error can be detected, its position can be specified and that error can be corrected. COPYRIGHT: (C)1997,JPO | ||||||
| 163 | Substitution of symbols, how to decode the block coding Metsuseji given that the employer influence on the insertion and deletion and equipment | JP11842088 | 1988-05-17 | JPH0648808B2 | 1994-06-22 | ジアンカルロ・ピラーニ; ジオルジオ・タリツコ |
| 164 | JPH0461374B2 - | JP26191587 | 1987-10-19 | JPH0461374B2 | 1992-09-30 | AABIN MOTEIBIHAI PATERU; DEBITSUDO TAA UEI WANGU; UERINGUTON CHAAPIIA JU |
| 165 | Sum decoding circuit | JP9263890 | 1990-04-06 | JPH03291033A | 1991-12-20 | IWANE YASUSHI |
| PURPOSE: To interrupt error propagation and to improve the error rate characteristic by inserting a known data in a data string before transmission difference conversion and using the known data as a feedback data in matching with a reception timing. CONSTITUTION: A clock regenerating circuit 10 regenerates a clock signal (h) from an input signal (c) and a frame regenerating circuit 11 generates a frame synchronizing signal (f) from the signals c, h. The signal (f) is inputted to a data selector 13 and known data reception timing generating circuit 12. The circuit 12 counts the signal (f) and when the count and a binary number representing the position of a known symbol are coincident, a known data reception timing signal (g) is outputted to the selector 13. The signals f, g are both at an L level at the normal data reception and the selector 13 selects a data e1 among data inputs e1-e3, a 1-bit decoding data is outputted to an EX-OR 8, in which decoding is implemented. When the level of the signal (f) is at an H level, the data e2 is selected and when the signal (g) is at an H, the data e3 is selected, a correct decoding data is inputted to a decoding circuit and propagation of error is interrupted. COPYRIGHT: (C)1991,JPO&Japio | ||||||
| 166 | JPS6363927B2 - | JP2321384 | 1984-02-08 | JPS6363927B2 | 1988-12-09 | |
| 167 | JPS6362774B2 - | JP2118384 | 1984-02-08 | JPS6362774B2 | 1988-12-05 | |
| 168 | JPS6322697B2 - | JP3083382 | 1982-02-26 | JPS6322697B2 | 1988-05-12 | YODA MASAAKI; KITAWAKI NOBUHIKO |
| PURPOSE:To reduce waveform distortion due to an error, by allotting the code error protection bit length of the code of a forecasted residual uniformly according to a prescribed value. CONSTITUTION:The deviation of the electric power or amplitude of an input signal in the direction of either frequency or time is detected and according to the detection result, the adaptive forecast encoding 2 of the input signal is performed by using variable information bit length. Then a decision 5 on the code error protection bit corresponding to the code sequence of the encoded forecasted residual is made according to the deviation of the signal electric power or amplitude. The above mentioned decision is so made that the waveform distortion due to a code error is minimized. On the basis of the variable protection bit length and variable information bit length, transmission line encoding 6 using an error correction code is carried out to send the signal to a transmission line 7. | ||||||
| 169 | Burst error detection method | JP500985 | 1985-01-17 | JPS61164352A | 1986-07-25 | KAWABE MANABU; SATO TAKURO; AKIYAMA HARUHIKO; FUKAZAWA ATSUSHI |
| PURPOSE:To supervise the quality of line by measuring the length of a burst error and the length of an error free section base on an error detection signal obtained by error correction. CONSTITUTION:An input terminal 1 is connected to the input of a code section 2 and an output of the code part 2 is connected to a communication line 4 by a transmission terminal 3. A reception terminal 5 of the communication line 4 is connected to the input of a decoding part 6, a data output signal 7 from the decoding part 6 is fed to an output terminal 6 and an error detection signal 9 is fed to the input of a burst length measuring part 10. The burst length measuring part 10 measures the length of a burst error and the length of an error free section based on an error detection signal 9 of the decoding part 6 and gives output to a burst length output terminal 11 and an error free length output terminal 12. | ||||||
| 170 | Digital signal transmission system | JP12209184 | 1984-06-15 | JPS612439A | 1986-01-08 | YASUDA YUTAKA; HIRATA YASUO |
| PURPOSE:To obtain easily an error correction effect almost equivalent to that of a low encoding ratio code of which encoding ratio is 1/m that of an original code through a simple encoder/decoder by decoding equivalently a code having k/nm encoding ratio to a code having k/n encoding ratio by m-times of multiplex-transmission at transmission side and averaging operation at reception side. CONSTITUTION:An input data string 1 having R data speed is converted into an encoded data string 3 by an original code encoder 2 and the data string 3 is sent to an m-times multiplexer 4 for an encoded bit. At that time, the data speed is n/k times which is the reciprocal of k/n encoding ratio. A transmission data string 5 having the data speed of m-times that of the encoded data string 3 is formed by multiplexing each encoded bit included in the data string 3 repeatedly m times through the m-times multiplexer 4 and a transmission signal 7 modulated by a modulator 6 is sent to a transmission line. On the receiving side, a base band signal sample value 10 obtained by demodulating a receiving signal 8 by a demodulator 9 is averaged by an m-bit averaging circuit 11 and a decoder input data string 12 to be inputted to an original code decoder 13 is formed on the basis of said average value. | ||||||
| 171 | Error correcting device for hagelbarger code | JP2321384 | 1984-02-08 | JPS60167040A | 1985-08-30 | KUME ATSUYA |
| PURPOSE:To improve the probability of correction of an actual information section even if an error occurs to an additional bit section by deciding on the specific pattern of the head part of a code and then calculating parity. CONSTITUTION:It is known that the starting six bits of data at the head part of the code are 0, so a parity AND gate control circuit 9 closes AND circuits 10 and 11. A control circuit 9 counts the number of send data and opens the AND gates 10 and 11 when read data arrives at the AND gates. Therefore, an error occurring to the head part of the code never causes a failure in correcting other parts and a failure in correcting the actual error occurrence position resulting from that the six bits which are 0 are judged as 1. | ||||||
| 172 | Diagnosis circuit for error correction circuit | JP7449383 | 1983-04-27 | JPS59200349A | 1984-11-13 | KOBAYASHI HIDEHIKO |
| PURPOSE:To set easily all correctable error patterns for correction of errors by modifying the write information and an error correction code with a control signal for error generation to produce an artificial error. CONSTITUTION:The input information is fed to an error correction generating circuit 1, and an error correction code is outputted together with the input information. An artificial fault generating circuit 2 supplies the input information and the error correction code to produce artificially an error. The output of the circuit 2 is written to a memory circuit 3. The data read out of the circuit 3 is subjected with the error correction, if any, at an error correction circuit 4. If no error contained in the data, this data is outputted as it is to outside as the read information. | ||||||
| 173 | PUNCTURING FOR STRUCTURED LOW DENSITY PARITY CHECK (LDPC) CODES | EP16763376.7 | 2016-08-23 | EP3375114A1 | 2018-09-19 | KUDEKAR, Shrinivas; PARK, Se Yong; MANOLAKOS, Alexandros; MUKKAVILLI, Krishna Kiran; LONCKE, Vincent; SORIAGA, Joseph Binamira; JIANG, Jing; RICHARDSON, Thomas Joseph |
| Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word | ||||||
| 174 | SIGNAL PROCESSING SYSTEM, METHOD AND DEVICE | EP15909463.0 | 2015-11-30 | EP3373536A1 | 2018-09-12 | LIU, Ling; XIAO, Zhiyu; LI, Liangchuan |
A signal processing system and method, and an apparatus are provided. A phase recovery apparatus may be used to: receive a feedback signal fed back by an information iteration apparatus, perform, based on the feedback signal, phase recovery on a signal output by an equalizer, and output a phase-recovered signal to a post filtering apparatus, so that the post filtering apparatus performs noise filtering on the phase-recovered signal, and outputs a noise-filtered signal to the information iteration apparatus. To be specific, the phase recovery may be performed, based on the signal fed back by the information iteration apparatus, on the signal output by the equalizer. Because output of the information iteration apparatus is more accurate in determining the signal, precision of the phase recovery can be improved, cycle skipping is reduced, and input signal quality of the post filtering apparatus is improved. Therefore, a problem that performance improvement of an entire system is limited because an existing turbo iteration manner cannot improve or cannot greatly improve input signal quality of a post filter can be resolved, and system performance is improved. |
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| 175 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING | EP12758086.8 | 2012-03-12 | EP2686850B1 | 2018-08-01 | HELM, Mark A.; CHANDRASEKHAR, Uday |
| Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | ||||||
| 176 | ROBUST SERDES WRAPPER | EP15827984 | 2015-07-29 | EP3143698A4 | 2018-05-23 | BUEHLER ERIK |
| Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so that the lane can be reset. Error correction can be provided by reconstructing the bit data in the invalid SerDes lane based on parity information in an optional parity lane. | ||||||
| 177 | A METHOD FOR UTILIZING AVAILABLE RESOURCES IN A COMMUNICATIONS NETWORK | EP15796994 | 2015-05-13 | EP3146775A4 | 2018-04-11 | RAINISH DORON |
| A method is described for use in a satellite communication network, utilizing available resources (e.g. when operating in an idle mode) of at least one first terminal. that belongs to a cluster comprising a plurality of terminals that are adapted to communicate with a satellite, by at least one other terminal being a second terminal that belongs to that cluster of terminals, and wherein the utilization of idle resources is done by enabling communications between the first and second terminals is carried out by using a communication link that is not part of the satellite communication network. | ||||||
| 178 | MULTI-WIRE SYMBOL TRANSITION CLOCKING SYMBOL ERROR CORRECTION | EP15805713.3 | 2015-11-24 | EP3224977A1 | 2017-10-04 | SENGOKU, Shoichiro |
| Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver. | ||||||
| 179 | Variable rate coding for forward link | EP10183999.1 | 2000-11-16 | EP2293481B1 | 2016-11-09 | Proctor, James A,. Jr. |
| 180 | Variable rate coding for forward link | EP10183999.1 | 2000-11-16 | EP2293481A3 | 2013-03-13 | Proctor, James A,. Jr. |
A technique for encoding a signal used in a digital communication system in which individual traffic channel data rates may be adapted to specific channel conditions. In particular, a forward error correction coding rate is adapted for individual channels while at the same time maintaining a fixed block size independent of the FEC coding rate. This allows the system data rate to adapt to the channel conditions experienced by a specific user. Thus, users experiencing good communication conditions with low multipath distortion may be allocated higher capacity, whereas users with significant multipath distortion may make use of lower rate (higher levels of coding) error codes to maintain high quality. Messages are sent from a transmitter to a receiver to inform the receiver of the coding rate implemented at any given point in time. These parameters may be adjusted independent of tranmitted power level through the expedient of ensuring that size of a transmitted frame remains constant, while permitting the ability to changeFEC coding rates and FEC block sizes.
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