| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 241 | Fail-safe error correction code system | JP2118384 | 1984-02-08 | JPS60167039A | 1985-08-30 | TAKAHASHI YUUJI; NAKAYAMA SHIYUNICHI |
| PURPOSE:To disable correction to a code with danger-side information and provide a fail-safe by setting a large/small relation between error correction codes previously, and preventing correction from a small signal to a large signal. CONSTITUTION:Circular blank parts in the center are areas where no error occurs and hatched parts encircled specified with dotted circles are area where errors are correctable. Then, only correction to a safety side is allowed as to patterns of transition to the correctable area of a different code among patterns of transition on transmission lines of a code part Fd(x) with danger information and a code part Fs(x) with safety information. For example, when 0 is converted into 0000 and 1 is converted into 1111, the number of each digit constituting 1 is much larger than that of each digit constituting 0. Namely, Fd(x)>F3(x). Thus, an error correction code is constituted and correction from 1 to 0 is allowed while correction from 0 to 1 is inhibited. | ||||||
| 242 | Error correction coding system | JP5344382 | 1982-03-31 | JPS58169642A | 1983-10-06 | SAKO YOUICHIROU |
| PURPOSE:To reduce substantially the effect of a transmission error, by providing a digital data having a high degree of importance at the position where the probability is small for incapability of error correction. CONSTITUTION:Respective high-order and low-order 8 bits are supplied through input terminals I0-I5 for continuous two samples among audio PCM signal series. These input signals are delayed by delaying units 1-14, and the error correction code series are delivered. Then data having a high degree of importance is allotted to the channel of a terminal part where the amount of delay is decreased or increased among the channels of plural digital data incorporated in the error correction code series. | ||||||
| 243 | Encoding means of error-correctable adaptive forecast | JP3083382 | 1982-02-26 | JPS58147255A | 1983-09-02 | YODA MASAHIKO; KITAWAKI NOBUHIKO |
| PURPOSE:To reduce waveform distortion due to an error, by allotting the code error protection bit length of the code of a forecasted residual uniformly according to a prescribed value. CONSTITUTION:The deviation of the electric power or amplitude of an input signal in the direction of either frequency or time is detected and according to the detection result, the adaptive forecast encoding 2 of the input signal is performed by using variable information bit length. Then a decision 5 on the code error protection bit corresponding to the code sequence of the encoded forecasted residual is made according to the deviation of the signal electric power or amplitude. The above mentioned decision is so made that the waveform distortion due to a code error is minimized. On the basis of the variable protection bit length and variable information bit length, transmission line encoding 6 using an error correction code is carried out to send the signal to a transmission line 7. | ||||||
| 244 | JPS558856B2 - | JP11831674 | 1974-10-16 | JPS558856B2 | 1980-03-06 | |
| 245 | JPS5085201A - | JP11831674 | 1974-10-16 | JPS5085201A | 1975-07-09 | |
| 246 | BASE STATION | EP16799625.5 | 2016-03-01 | EP3300422A1 | 2018-03-28 | UCHINO, Tooru; HAPSARI, Wuri Andarmawanti; UMESH, Anil; TAKAHASHI, Hideaki; ABETA, Sadayuki |
A base station is provided. The base station is used as a first base station in a mobile communication system including the first base station, a second base station communicating with the first base station, and a user apparatus communicating with the first base station. The base station includes a first reception unit configured to receive from the second base station a process ID used for error correction processing; a second reception unit configured to receive data from the user apparatus; and a transmission unit configured to transmit the data and the process ID to the second base station in the case where the data is received from the user apparatus. |
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| 247 | ERROR CORRECTION IN A STACKED MEMORY | EP10841595.1 | 2010-12-22 | EP2521972B1 | 2018-01-24 | JEDDELOH, Joe M. |
| Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed. | ||||||
| 248 | ERROR DETECTION CONSTANTS OF SYMBOL TRANSITION CLOCKING TRANSCODING | EP15816567.0 | 2015-11-24 | EP3224979A1 | 2017-10-04 | SENGOKU, Shoichiro |
| Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver. | ||||||
| 249 | Variable rate decoding for forward link | EP09173620.7 | 2000-11-16 | EP2141850B1 | 2017-08-02 | Proctor, James A,. Jr. |
| 250 | A METHOD FOR UTILIZING AVAILABLE RESOURCES IN A COMMUNICATIONS NETWORK | EP15796994.0 | 2015-05-13 | EP3146775A1 | 2017-03-29 | RAINISH, Doron |
| A method is described for use in a satellite communication network, utilizing available resources (e.g. when operating in an idle mode) of at least one first terminal. that belongs to a cluster comprising a plurality of terminals that are adapted to communicate with a satellite, by at least one other terminal being a second terminal that belongs to that cluster of terminals, and wherein the utilization of idle resources is done by enabling communications between the first and second terminals is carried out by using a communication link that is not part of the satellite communication network. | ||||||
| 251 | SYSTEM AND METHOD FOR APRIORI DECODING | EP13864415 | 2013-12-18 | EP2926474A4 | 2016-02-17 | CALLARD AARON; BALIGH MOHAMMADHADI; AU KELVIN KAR KIN |
| Embodiments are provided for transmitting channel information, such as control channel information, using lower resources at the transmitter combined with using apriori information associated with channel information in the decoder of the receiver. The apriori information represent predictable information that can be predicted by the receiver and is not transmitted with the channel information by the transmitter. The transmitter determines the apriori information for the channel and codes the channel information into bits and fields excluding the apriori information. Upon receiving the channel information, the receiver determines the apriori information associated in accordance with previously received information. The apriori information is then provided as probability information for input to the decoder. The decoder then decodes the received information in accordance with the apriori information. | ||||||
| 252 | DECODING METHOD AND DECODING DEVICE | EP12732365 | 2012-02-14 | EP2611038A4 | 2015-04-01 | LI YANG; JIN LILI; ZHAO YU; XIAO ZHIYU |
| 253 | METHOD FOR GENERATING FORWARD ERROR CORRECTION PACKET IN MULTIMEDIA SYSTEM AND METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING FORWARD ERROR CORRECTION PACKET | EP12812110 | 2012-07-06 | EP2730052A4 | 2015-02-25 | HWANG SUNG-HEE; HWANG SUNG-OH; MYUNG SEHO; YANG HYUN-KOO; PARK KYUNG-MO |
| A method and apparatus for transmitting a Forward Error Correction (FEC) packet block including a plurality of FEC packets in a multimedia system are provided. The method includes generating a plurality of first FEC packet blocks by performing a first FEC encoding on a plurality of source symbols, each of the plurality of first FEC packet blocks including at least one source packet and at least one repair packet for repair of each of the at least one source packet, generating a second FEC packet block by performing a second FEC encoding on the plurality of first FEC packet blocks, the second FEC packet block including at least one repair packet for the plurality of first FEC packet blocks, and transmitting the second FEC packet block that includes, in header information of each of the at least one source packet and the at least one repair packet. | ||||||
| 254 | RANK-SPECIFIC CYCLIC REDUNDANCY CHECK | EP12807403 | 2012-06-28 | EP2727115A4 | 2015-02-18 | SUBASHCHANDRABOSE RAMESH; THOMAS TESSIL; MITRA SAMBARAN; DAS DEBALEENA; CHENG KAI |
| Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems. | ||||||
| 255 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING | EP12758086 | 2012-03-12 | EP2686850A4 | 2015-01-28 | HELM MARK A; CHANDRASEKHAR UDAY |
| Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | ||||||
| 256 | RANK-SPECIFIC CYCLIC REDUNDANCY CHECK | EP12807403.6 | 2012-06-28 | EP2727115A2 | 2014-05-07 | SUBASHCHANDRABOSE, Ramesh; THOMAS, Tessil; MITRA, Sambaran; DAS, Debaleena; CHENG, Kai |
| Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems. | ||||||
| 257 | ERROR CORRECTION IN A STACKED MEMORY | EP10841595 | 2010-12-22 | EP2521972A4 | 2014-02-19 | JEDDELOH JOE M |
| Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed. | ||||||
| 258 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING | EP12758086.8 | 2012-03-12 | EP2686850A1 | 2014-01-22 | HELM, Mark A.; CHANDRASEKHAR, Uday |
| Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | ||||||
| 259 | ERROR CORRECTION IN A STACKED MEMORY | EP10841595.1 | 2010-12-22 | EP2521972A2 | 2012-11-14 | JEDDELOH, Joe M. |
| Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed. | ||||||
| 260 | FORWARD ERROR CORRECTION ENCODING FOR MULTIPLE LINK TRANSMISSION COMPATIBLE WITH 64B/66B SCRAMBLING | EP07821012.7 | 2007-10-08 | EP2095557B1 | 2010-08-18 | DELL, Timothy, Jay; GLAISE, Rene |
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