Sum decoding circuit专利检索- .用数据表示中的冗余项检错或前向纠错即码字包含比源字更多的位数专利检索查询-专利查询网

Sum decoding circuit
申请号	JP9263890	申请日	1990-04-06	公开(公告)号	JPH03291033A	公开(公告)日	1991-12-20
申请人	Mitsubishi Electric Corp;			发明人	IWANE YASUSHI;
摘要	PURPOSE: To interrupt error propagation and to improve the error rate characteristic by inserting a known data in a data string before transmission difference conversion and using the known data as a feedback data in matching with a reception timing. CONSTITUTION: A clock regenerating circuit 10 regenerates a clock signal (h) from an input signal (c) and a frame regenerating circuit 11 generates a frame synchronizing signal (f) from the signals c, h. The signal (f) is inputted to a data selector 13 and known data reception timing generating circuit 12. The circuit 12 counts the signal (f) and when the count and a binary number representing the position of a known symbol are coincident, a known data reception timing signal (g) is outputted to the selector 13. The signals f, g are both at an L level at the normal data reception and the selector 13 selects a data e1 among data inputs e1-e3, a 1-bit decoding data is outputted to an EX-OR 8, in which decoding is implemented. When the level of the signal (f) is at an H level, the data e2 is selected and when the signal (g) is at an H, the data e3 is selected, a correct decoding data is inputted to a decoding circuit and propagation of error is interrupted. COPYRIGHT: (C)1991,JPO&Japio
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