Integrated viterbi decoder and method for testing the same专利检索- .编码理论基本假设;编码约束;误差概率估算方法;信道模型;代码的模拟或测试专利检索查询-专利查询网

Integrated viterbi decoder and method for testing the same
申请号	EP86115031.6	申请日	1986-10-29	公开(公告)号	EP0221507A3	公开(公告)日	1989-01-18
申请人	FUJITSU LIMITED;			发明人	Shimoda, Kaneyasu; Yamashita, Atsushi; Katoh, Tadayoshi;
摘要	An integrated viterbi decoder structure and method, in which the viterbi decoder receives test input signals at a distributor (l), an ACS circuit (2) and a path memory (3) and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder.
权利要求
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