| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | Constant transconductance bias circuit | US14640960 | 2015-03-06 | US09413297B2 | 2016-08-09 | Yu-Jiu Wang; Ching-Yun Chu |
| A bias circuit is adapted for biasing a to-be-biased transconductance cell such that the to-be-biased transconductance cell has a constant transconductance, and includes a converter and a controller. The converter receives first and second current signals, and generates, based on the first and second current signals, a first voltage signal, a second voltage signal and a bias voltage that is for biasing the to-be-biased transconductance cell. The controller receives the first and second voltage signals from the converter, generates the first and second current signals for the converter based on the first and second voltage signals so as to make a magnitude of the first voltage signal equal a magnitude of the second voltage signal. | ||||||
| 82 | AMPLIFIER WITH BASE CURRENT REUSE | US14855058 | 2015-09-15 | US20160087589A1 | 2016-03-24 | Philip John Lehtola |
| An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module. | ||||||
| 83 | BIAS ADJUSTMENT CIRCUITRY FOR BALANCED AMPLIFIERS | US14461905 | 2014-08-18 | US20160049907A1 | 2016-02-18 | Kyle Baker |
| Circuitry includes a balanced amplifier and bias adjustment circuitry. The bias adjustment circuitry is coupled to the balanced amplifier and is configured to measure an RF termination voltage across an output termination impedance of the balanced amplifier and adjust a bias voltage supplied to the balanced amplifier based on the RF termination voltage. Notably, the RF termination voltage is proportional to a voltage standing wave ratio (VSWR) of the balanced amplifier, and thus enables an accurate measurement thereof. By using the RF termination voltage to adjust a bias voltage supplied to the balanced amplifier, overvoltage and/or thermally stressing conditions of the balanced amplifier as a result of high VSWR may be avoided while simultaneously avoiding the need for large or expensive isolation circuitry. | ||||||
| 84 | Circuits and methods for power amplification with extended high efficiency | US14088321 | 2013-11-22 | US09231527B2 | 2016-01-05 | Joonhoi Hur; Paul Joseph Draxler |
| The present disclosure includes circuits and methods for power amplifiers. In one embodiment, a main and peaking amplifier receive dynamic power supply voltages to operate an RF power amplifier in a high efficiency range for a particular output voltage. The power supply voltages may be changed based on an output voltage so that the power amplifier operates within a high efficiency plateau. In one embodiment, different discrete power supply voltage levels are used for different output voltage ranges. In another embodiment, a continuous time varying power supply voltage is provided as the power supply voltage. A dynamic supply voltage may be generated having a lower frequency than a signal path of the power amplifier. | ||||||
| 85 | LOW NOISE AMPLIFIER FOR MEMS CAPACITIVE TRANSDUCERS | US14700666 | 2015-04-30 | US20150318829A1 | 2015-11-05 | Santosh Astgimath |
| This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit (40) is provided which includes a feedback path from its output node (Nout) to a control bias node (BC) in order to provide a preamplifier signal gain that may be greater than unity. A first transistor (M1) is configured to have its gate node connected to an input node (NIN) for receiving the input signal (VIN) and its drain node connected to an input node (X) of an output stage (A). The source node of the first transistor is connected to the output node (NOUT). A current source (I2) is configured to deliver a current to the drain node of the first transistor (M1), wherein the current source (I2) is controlled by a bias control voltage (VBC) at the bias control node (BC). A feedback impedance network (Z1) comprising a first port connected to the output node (NOUT) and a second port connected to the bias control node (BC) is provided. | ||||||
| 86 | CONSTANT TRANSCONDUCTANCE BIAS CIRCUIT | US14640960 | 2015-03-06 | US20150256131A1 | 2015-09-10 | Yu-Jiu Wang; Ching-Yun CHU |
| A bias circuit is adapted for biasing a to-be-biased transconductance cell such that the to-be-biased transconductance cell has a constant transconductance, and includes a converter and a controller. The converter receives first and second current signals, and generates, based on the first and second current signals, a first voltage signal, a second voltage signal and a bias voltage that is for biasing the to-be-biased transconductance cell. The controller receives the first and second voltage signals from the converter, generates the first and second current signals for the converter based on the first and second voltage signals so as to make a magnitude of the first voltage signal equal a magnitude of the second voltage signal. | ||||||
| 87 | VARIABLE GAIN MULTISTAGE AMPLIFIER AND RECEIVER | US14626938 | 2015-02-20 | US20150249437A1 | 2015-09-03 | YOHEI MORISHITA; RYO KITAMURA; NORIAKI SAITO |
| There is provided a variable gain multistage amplifier including: an input terminal to which the input signal is input; multistage amplifiers amplify the input signal, the multistage amplifiers being connected in series; and an output terminal that outputs the amplified signal, and the multistage amplifiers include one or more successive cascode amplifiers, one of which is in final stage. | ||||||
| 88 | MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING | US14532816 | 2014-11-04 | US20150123728A1 | 2015-05-07 | David M. SIGNOFF; Ming HE; Wayne A. LOEB |
| A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. | ||||||
| 89 | Temperature compensating device and satellite signal receiving system | US13092133 | 2011-04-21 | US08884816B2 | 2014-11-11 | Chen-Chia Huang; Chun-Ching Wang; Cho-Hsuan Wu |
| A temperature compensating device for providing active bias for an amplifier includes a voltage source, a plurality of loads, and a current generator for generating a current for the amplifier according to voltages provided by the voltage source and the plurality of loads, wherein a first load of the plurality of loads is a thermistor utilized for keeping the current within a specified range under a plurality of ambient temperatures. | ||||||
| 90 | DUAL USE TRANSISTOR | US13387311 | 2010-07-16 | US20120139644A1 | 2012-06-07 | Sever Cercelaru |
| A circuit for amplifying radio frequency signals comprising: a terminal for connection to an antenna; a common amplifier arranged in a common-gate configuration between a first node and said terminal; a transmit amplifier operable to amplify a radio frequency signal present at an input node and provide the amplified signal to said first node; and a receive amplifier operable to amplify a radio frequency signal present at said first node and provide the amplified signal to an output node; wherein the circuit is operable in two modes: in a receive mode, the common and receive amplifiers being configured so as to together form a receive cascode for amplifying radio frequency signals received at the terminal; and in a transmit mode, the common and transmit amplifiers being configured so as to together form a transmit cascode for amplifying radio frequency signals applied at the input node. | ||||||
| 91 | Field effect transistor amplifier with linearization | US10920526 | 2004-08-17 | US07853235B2 | 2010-12-14 | Vladimir Aparin |
| An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance. | ||||||
| 92 | High-power common-base amplifier employing current source output bias | US12233307 | 2008-09-18 | US07830208B2 | 2010-11-09 | Zhenqiang Ma; Guogong Wang; Guoxuan Qin |
| A common-base amplifier for a bipolar junction transistor or a heterojunction bipolar transistor employs an active current source output biasing to provide for improved power output in a power saturation region providing increased power for a given transistor area such as may be advantageous in mobile radio transmitters or the like. | ||||||
| 93 | Stacked buffers | US11498994 | 2006-08-04 | US07821296B2 | 2010-10-26 | Lawrence A. Singer; Ronald A. Kapusta, Jr. |
| Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit. | ||||||
| 94 | SYSTEM AND METHOD FOR DYNAMIC DRAIN VOLTAGE ADJUSTMENT TO CONTROL LINEARITY, OUTPUT POWER, AND EFFICIENCY IN RF POWER AMPLIFIERS | US12790838 | 2010-05-30 | US20100237948A1 | 2010-09-23 | Dung C. Nguyen; Soon Yoon; Ahmad Khanifar; Don C. Devendorf |
| A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency. | ||||||
| 95 | Amplifier circuit, semiconductor device, and controlling method | US11985970 | 2007-11-19 | US07663440B2 | 2010-02-16 | Kenji Komori; Atsushi Hirabayashi |
| An amplifier circuit including a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits connected in parallel with each other. The CMOS inverter circuits each include a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, gates of the first PMOS and NMOS transistors, a second PMOS transistor, a first switch connected to a gate of the second PMOS transistor, a second NMOS transistor, and a second switch connected to a gate of the second NMOS transistor. | ||||||
| 96 | Bonded Wafer Package Module | US12124925 | 2008-05-21 | US20090289722A1 | 2009-11-26 | Hans Dropmann; Uppili Sridhar; Carlton Stuebing |
| Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed. | ||||||
| 97 | Amplifier circuit, semiconductor device, and controlling method | US11985970 | 2007-11-19 | US20080136524A1 | 2008-06-12 | Kenji Komori; Atsushi Hirabayashi |
| An amplifier circuit including a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits connected in parallel with each other. The CMOS inverter circuits each include a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, gates of the first PMOS and NMOS transistors, a second PMOS transistor, a first switch connected to a gate of the second PMOS transistor, a second NMOS transistor, and a second switch connected to a gate of the second NMOS transistor. | ||||||
| 98 | Stacked buffers | US11498994 | 2006-08-04 | US20080030233A1 | 2008-02-07 | Lawrence A. Singer; Ronald A. Kapusta |
| Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit. | ||||||
| 99 | Rail-to-rail source followers | US11142176 | 2005-05-31 | US07208974B1 | 2007-04-24 | Siew Yong Chui |
| Circuits and methods are provided for producing a rail-to-rail output voltage. A circuit includes a level shifter, a source follower, and a current compensation circuit. The level shifter receives an input signal and applies a compensation voltage to the input signal relative to a voltage level of the input signal in steady-state. The source follower produces an output signal and, responsive to variations in the voltage level of the input signal, changes the voltage level of the output signal using a biasing current. The current compensation circuit, responsive to a difference between the voltage levels of the input and output signals, varies an amount of the biasing current. | ||||||
| 100 | Amplifying a signal using a control modulator that provides a bias resistance | US10977007 | 2004-10-28 | US07154337B2 | 2006-12-26 | Scott M. Heston |
| According to one embodiment of the present invention, an amplifier includes an amplifying transistor coupled to a ground and operable to amplify a received signal. One or more bias components provide a bias resistance for the amplifying transistor. The one or more bias components include a control modulator coupled in series between the amplifying transistor and the ground. The control modulator receives a control signal and modulates the amplifying transistor in response to the control signal. | ||||||
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