| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | Systems and methods providing an intermodulation distortion sink | US15472055 | 2017-03-28 | US10014845B2 | 2018-07-03 | Timothy Donald Gathman; Chirag Dipak Patel; Sasha Vujcic; Aleksandar Miodrag Tasic; Wu-Hsin Chen; Klaas van Zalinge |
| A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node. | ||||||
| 22 | LNA with Programmable Linearity | US15895863 | 2018-02-13 | US20180175807A1 | 2018-06-21 | Hossein Noori; Chih-Chieh Cheng |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 23 | Amplifier with base current reuse | US15418434 | 2017-01-27 | US09991850B2 | 2018-06-05 | Philip John Lehtola |
| An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module. | ||||||
| 24 | LNA with Programmable Linearity | US15272103 | 2016-09-21 | US20180083579A1 | 2018-03-22 | Hossein Noori; Chih-Chieh Cheng |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 25 | Integrated Circuit Arrangement for a Microphone, Microphone System and Method for Adjusting One or More Circuit Parameters of the Microphone System | US15548371 | 2015-02-27 | US20180034431A1 | 2018-02-01 | Gino Rocca; Tomasz Hanzlik |
| An integrated circuit arrangement for a microphone, a microphone system and a method for adjusting circuit parameters of the microphone are disclosed. In an embodiment an integrated circuit includes an amplifier circuit with a first switchable network circuit for adjusting an amplifier current of the amplifier circuit, the first switchable network circuit comprising a plurality of switches (SW1, . . . ,SWx) each coupled with a first control port of the first switchable network circuit and a control unit coupled with the first control port of the first switchable network circuit and configured to control a setting of the respective switches (SW1, . . . ,SWx) of the first switchable network circuit. | ||||||
| 26 | Low noise amplifier for MEMS capacitive transducers | US14700666 | 2015-04-30 | US09729114B2 | 2017-08-08 | Santosh Astgimath |
| This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit (40) is provided which includes a feedback path from its output node (Nout) to a control bias node (BC) in order to provide a preamplifier signal gain that may be greater than unity. A first transistor (M1) is configured to have its gate node connected to an input node (NIN) for receiving the input signal (VIN) and its drain node connected to an input node (X) of an output stage (A). The source node of the first transistor is connected to the output node (NOUT). A current source (I2) is configured to deliver a current to the drain node of the first transistor (M1), wherein the current source (I2) is controlled by a bias control voltage (VBC) at the bias control node (BC). A feedback impedance network (Z1) comprising a first port connected to the output node (NOUT) and a second port connected to the bias control node (BC) is provided. | ||||||
| 27 | Baseband filters and interfaces between a digital-to-analog converter and a baseband filter | US14941419 | 2015-11-13 | US09647639B1 | 2017-05-09 | Ibrahim Chamas |
| Exemplary embodiments of the present disclosure are related to baseband filters. A device may include a digital-to-analog converter (DAC) configured to output a DC current. The device may also include an operational amplifier coupled to an output of the DAC and configured to bias an input stage of the operational amplifier with the DC current. | ||||||
| 28 | Bias adjustment circuitry for balanced amplifiers | US14461905 | 2014-08-18 | US09595927B2 | 2017-03-14 | Kyle Baker |
| Circuitry includes a balanced amplifier and bias adjustment circuitry. The bias adjustment circuitry is coupled to the balanced amplifier and is configured to measure an RF termination voltage across an output termination impedance of the balanced amplifier and adjust a bias voltage supplied to the balanced amplifier based on the RF termination voltage. Notably, the RF termination voltage is proportional to a voltage standing wave ratio (VSWR) of the balanced amplifier, and thus enables an accurate measurement thereof. By using the RF termination voltage to adjust a bias voltage supplied to the balanced amplifier, overvoltage and/or thermally stressing conditions of the balanced amplifier as a result of high VSWR may be avoided while simultaneously avoiding the need for large or expensive isolation circuitry. | ||||||
| 29 | AMPLIFIER WITH COMPENSATION OF GAIN IN LOW FREQUENCIES | US15136644 | 2016-04-22 | US20160329869A1 | 2016-11-10 | Keiji TANAKA; Yoshiyuki SUGIMOTO |
| An amplifier includes a differential amplifier and a compensator. A differential amplifier includes a current source and paired transistors. The paired transistors generate an output signal by dividing a source current supplied by the current source into emitter currents of the paired transistors in response to a difference between an input signal and a reference signal. A compensator includes an amplifying transistor and a feedback circuit that feeds a collector current output from a collector of the amplifying transistor back to a base of the amplifying transistor therethrough. The compensator generates the reference signal at a base of the amplifying transistor. The compensator decreases power consumption of the amplifying transistor when the collector current increases, and increases the power consumption of the amplifying transistor when the collector current decreases. The compensator suppresses a peaking of gain in a low frequency band. | ||||||
| 30 | Variable gain multistage amplifier and receiver | US14626938 | 2015-02-20 | US09369103B2 | 2016-06-14 | Yohei Morishita; Ryo Kitamura; Noriaki Saito |
| There is provided a variable gain multistage amplifier including: an input terminal to which the input signal is input; multistage amplifiers amplify the input signal, the multistage amplifiers being connected in series; and an output terminal that outputs the amplified signal, and the multistage amplifiers include one or more successive cascode amplifiers, one of which is in final stage. | ||||||
| 31 | CIRCUITS AND METHODS FOR POWER AMPLIFICATION WITH EXTENDED HIGH EFFICIENCY | US14088321 | 2013-11-22 | US20150145600A1 | 2015-05-28 | Joonhoi Hur; Paul J. Draxler |
| The present disclosure includes circuits and methods for power amplifiers. In one embodiment, a main and peaking amplifier receive dynamic power supply voltages to operate an RF power amplifier in a high efficiency range for a particular output voltage. The power supply voltages may be changed based on an output voltage so that the power amplifier operates within a high efficiency plateau. In one embodiment, different discrete power supply voltage levels are used for different output voltage ranges. In another embodiment, a continuous time varying power supply voltage is provided as the power supply voltage. A dynamic supply voltage may be generated having a lower frequency than a signal path of the power amplifier. | ||||||
| 32 | Dual use transistor | US13387311 | 2010-07-16 | US08989679B2 | 2015-03-24 | Sever Cercelaru |
| A circuit for amplifying radio frequency signals comprising: a terminal for connection to an antenna; a common amplifier arranged in a common-gate configuration between a first node and said terminal; a transmit amplifier operable to amplify a radio frequency signal present at an input node and provide the amplified signal to said first node; and a receive amplifier operable to amplify a radio frequency signal present at said first node and provide the amplified signal to an output node; wherein the circuit is operable in two modes: in a receive mode, the common and receive amplifiers being configured so as to together form a receive cascode for amplifying radio frequency signals received at the terminal; and in a transmit mode, the common and transmit amplifiers being configured so as to together form a transmit cascode for amplifying radio frequency signals applied at the input node. | ||||||
| 33 | Method and system for providing automatic gate bias and bias sequencing for field effect transistors | US14149468 | 2014-01-07 | US08963643B2 | 2015-02-24 | Lloyd L Lautzenhiser |
| A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices. | ||||||
| 34 | Temperature Compensating Device and Satellite Signal Receiving System | US13092133 | 2011-04-21 | US20120194380A1 | 2012-08-02 | Chen-Chia Huang; Chun-Ching Wang; Cho-Hsuan Wu |
| A temperature compensating device for providing active bias for an amplifier includes a voltage source, a plurality of loads, and a current generator for generating a current for the amplifier according to voltages provided by the voltage source and the plurality of loads, wherein a first load of the plurality of loads is a thermistor utilized for keeping the current within a specified range under a plurality of ambient temperatures. | ||||||
| 35 | Bonded wafer package module | US12124925 | 2008-05-21 | US07863699B2 | 2011-01-04 | Hans Dropmann; Uppili Sridhar; Carlton Stuebing |
| Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed. | ||||||
| 36 | Rail-to-rail source followers | US11737085 | 2007-04-18 | US07463066B1 | 2008-12-09 | Siew Yong Chui |
| Circuits and methods are provided for producing a rail-to-rail output voltage. A circuit includes a level shifter and a source follower. The level shifter receives an input signal and applies a compensation voltage to the input signal relative to a voltage level of the input signal in steady-state. The source follower produces an output signal and, responsive to variations in the voltage level of the input signal, changes the voltage level of the output signal. | ||||||
| 37 | SYSTEM AND METHOD FOR DYNAMIC DRAIN VOLTAGE ADJUSTMENT TO CONTROL LINEARITY, OUTPUT POWER, AND EFFICIENCY IN RF POWER AMPLIFIERS | US12031249 | 2008-02-14 | US20080211583A1 | 2008-09-04 | Dung C. Nguyen; Soon Yoon; Ahmad Khanifar; Don C. Devendorf |
| A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency. | ||||||
| 38 | Semiconductor integrated circuit and radio communication apparatus using same | US10084318 | 2002-02-28 | US06999740B2 | 2006-02-14 | Takahiro Ogihara |
| An amplifier circuit unit including a signal amplifying transistor is provided with a first bypass circuit unit for bypassing a part of an input signal to a ground side according to the strength of the input signal, and a second bypass circuit unit for bypassing a part of the input signal to an output side according to the strength of the input signal, whereby gain attenuation control is effected. Also, the amplifier circuit unit is provided with a control circuit unit for decreasing the drain bias current of the signal amplifying transistor when the first bypass circuit unit bypasses the part of the input signal to the ground side, and interrupting the drain bias current of the signal amplifying transistor when the second bypass circuit unit bypasses the part of the input signal to the output side, whereby control of the drain bias current is effected. | ||||||
| 39 | Semiconductor integrated circuit and radio communication apparatus using same | US10084318 | 2002-02-28 | US20020119762A1 | 2002-08-29 | Takahiro Ogihara |
| An amplifier circuit unit including a signal amplifying is provided with a first bypass circuit unit for bypassing a part of an input signal to a ground side according to strength of the input signal, and a second bypass circuit unit for bypassing a part of the input signal to an output side according to the strength of the input signal, whereby gain attenuation control is effected. Also, the amplifier circuit unit is provided with a control circuit unit for decreasing a drain bias current of the signal amplifying when the first bypass circuit unit bypasses the part of the input signal to the ground side, and interrupting the drain bias current of the signal amplifying when the second bypass circuit unit bypasses the part of the input signal to the output side, whereby control of the drain bias current is effected. | ||||||
| 40 | INTEGRATED CIRCUIT ARRANGEMENT FOR A MICROPHONE, MICROPHONE SYSTEM AND METHOD FOR ADJUSTING ONE OR MORE CIRCUIT PARAMETERS OF THE MICROPHONE SYSTEM | EP15707350.3 | 2015-02-27 | EP3262849A1 | 2018-01-03 | ROCCA, Gino; HANZLIK, Tomasz |
| An integrated circuit arrangement for a microphone, a microphone system and a method for adjusting circuit parameters of the microphone are disclosed. In an embodiment an integrated circuit includes an amplifier circuit with a first switchable network circuit for adjusting an amplifier current of the amplifier circuit, the first switchable network circuit comprising a plurality of switches (SW1, . . . ,SWx) each coupled with a first control port of the first switchable network circuit and a control unit coupled with the first control port of the first switchable network circuit and configured to control a setting of the respective switches (SW1, . . . ,SWx) of the first switchable network circuit. | ||||||
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