| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | HIGH-POWER COMMON-BASE AMPLIFIER EMPLOYING CURRENT SOURCE OUTPUT BIAS | US12233307 | 2008-09-18 | US20100066454A1 | 2010-03-18 | Zhenqiang Ma; Guogong Wang; Guoxuan Qin |
| A common-base amplifier for a bipolar junction transistor or a heterojunction bipolar transistor employs an active current source output biasing to provide for improved power output in a power saturation region providing increased power for a given transistor area such as may be advantageous in mobile radio transmitters or the like. | ||||||
| 62 | Amplifier circuit having dynamically biased configuration | US12154648 | 2008-05-23 | US20090289716A1 | 2009-11-26 | Kent Jaeger; Lawrence E. Connell |
| Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively. | ||||||
| 63 | FIELD EFFECT TRANSISTOR AMPLIFIER WITH LINEARIZATION | US10920526 | 2004-08-17 | US20080242257A9 | 2008-10-02 | Vladimir Aparin |
| An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance. | ||||||
| 64 | Field effect transistor amplifier with linearization | US10920526 | 2004-08-17 | US20050176399A1 | 2005-08-11 | Vladimir Aparin |
| An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance. | ||||||
| 65 | Amplifier circuit, a transmitter and a wireless telephone | US19645 | 1998-02-06 | US5963095A | 1999-10-05 | Hendrik A. Visser |
| An amplifier circuit, particularly for RF-purposes includes a main current stream of a controllable RF-semiconductor device having a control input, a control means having a control output coupled to the control input for controlling the main current stream, and a compensation circuit having a compensation output coupled to the control input for compensating the controllable semiconductor device. The compensation circuit is constructed so as to be temporarily active during a period of time wherein the control means do not supply a control output signal to the control input of the controllable semiconductor device. This provides a suitable solution for IC's and for dealing with DC-adjustment disturbances in a low DC-current dissipating manner caused by a lack of pull-down capability when the amplifier circuit operates at very high frequencies or at relatively large amplitudes. | ||||||
| 66 | 차동 증폭기들 | KR1020177019329 | 2015-12-14 | KR1020170094401A | 2017-08-17 | 코르비쉴리필 |
| 차동증폭기는: 테일트랜지스터(10) 및트랜지스터들(6, 8)의차동쌍을포함하는롱 테일쌍 트랜지스터구성(2); 및복제전압을기준전압에일치시키기위해상기복제회로(4)내피드백전류를변화시키도록구성된복제회로(4)로서, 상기복제회로(4)내상기피드백전류를변화시키는것은상기롱 테일쌍(2)에동상모드전압을결정하기위해상기테일트랜지스터(10)를통과하는테일전류를제어하는상기롱 테일쌍에상기테일트랜지스터(10)에바이어스전압을제공하는, 상기복제회로를포함한다. | ||||||
| 67 | 증폭기 회로, 송신기 및 무선 전화기 | KR1019980707980 | 1998-01-15 | KR1020000064868A | 2000-11-06 | 비제르핸드릭아렌드 |
| 특히 RF 목적을위한증폭기회로는제어입력을갖는제어가능한 RF 반도체장치의주 전류흐름, 주전류흐름을제어하기위하여제어입력에연결된제어출력을갖는제어수단, 및제어가능한반도체장치를보상하기위하여제어입력에연결된보상출력을갖는보상회로포함한다. 보상회로는제어수단이제어가능한반도체장치의제어입력에제어출력신호를제공하지않는시간간격동안에일시적으로액티브영역에서동작하게되도록구성된다. 이것은증폭기회로가매우높은주파수에서동작하거나상대적으로큰 진폭으로동작할 때풀다운용량의부족으로야기되는낮은 DC 전류방산방식으로 IC장치와 DC 조정교란을취급하는데대한적합한해결책을제공한다. | ||||||
| 68 | MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING | EP14857354.6 | 2014-11-04 | EP3066753A1 | 2016-09-14 | SIGNOFF, David, M.; HE, Ming; LOEB, Wayne, A. |
| A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. | ||||||
| 69 | Amplifier with non-linear current mirror | EP11150119.3 | 2011-01-04 | EP2472723B1 | 2015-12-16 | Fiocchi, Carlo |
| 70 | DUAL USE TRANSISTOR | EP10734983.9 | 2010-07-16 | EP2449674B1 | 2014-07-02 | CERCELARU, Sever |
| 71 | STACKED BUFFERS | EP07810915.4 | 2007-07-31 | EP2047593B1 | 2014-07-02 | SINGER, Lawrence, A.; KAPUSTA, Ronald, A. |
| 72 | DUAL USE TRANSISTOR | EP10734983.9 | 2010-07-16 | EP2449674A1 | 2012-05-09 | CERCELARU, Sever |
| A circuit for amplifying radio frequency signals comprising: a terminal for connection to an antenna; a common amplifier arranged in a common-gate configuration between a first node and said terminal; a transmit amplifier operable to amplify a radio frequency signal present at an input node and provide the amplified signal to said first node; and a receive amplifier operable to amplify a radio frequency signal present at said first node and provide the amplified signal to an output node; wherein the circuit is operable in two modes: in a receive mode, the common and receive amplifiers being configured so as to together form a receive cascode for amplifying radio frequency signals received at the terminal; and in a transmit mode, the common and transmit amplifiers being configured so as to together form a transmit cascode for amplifying radio frequency signals applied at the input node. | ||||||
| 73 | System and method for dynamic drain voltage adjustment to control linearity, output power, and efficiency in RF power amplifiers | EP08151486.1 | 2008-02-15 | EP1959564A2 | 2008-08-20 | Nguyen, Dung C.; Yoon, Soon K.; Khanifar, Ahmad; Devendorf, Don. C. |
A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor (616) measuring ambient temperature of the PA, and an adaptive PA control processor (608) that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor (614) measures output power of the PA, and the control processor (608) dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency.
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| 74 | FET AMPLIFIER WITH ADJUSTABLE DEGENERATION RESISTANCE | EP05812729.1 | 2005-10-20 | EP1807929A1 | 2007-07-18 | HESTON, Scott, M. |
| An amplifier (64) comprises an amplifying field-effect transistor (70) having its source connected to ground via an adjustable degeneration resistance (80). A capacitor (76) is connected in parallel to the variable degeneration resistance (80). The degeneration resistance, comprising a field effect transistor, provides adjustable current feedback to the amplifying transistor (70) to stabilise the drain current of the amplifying transistor (70) at a desired value. | ||||||
| 75 | Systems and Methods Providing an Intermodulation Distortion Sink | US15472055 | 2017-03-28 | US20180048294A1 | 2018-02-15 | Timothy Donald Gathman; Chirag Dipak Patel; Sasha Vujcic; Aleksandar Miodrag Tasic; Wu-Hsin Chen; Klaas van Zalinge |
| A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node. | ||||||
| 76 | Method and system for providing automatic gate bias and bias sequencing for field effect transistors | US14626580 | 2015-02-19 | US09787271B2 | 2017-10-10 | Lloyd L Lautzenhiser |
| A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices. | ||||||
| 77 | Amplifier with compensation of gain in low frequencies | US15136644 | 2016-04-22 | US09660601B2 | 2017-05-23 | Keiji Tanaka; Yoshiyuki Sugimoto |
| An amplifier includes a differential amplifier and a compensator. A differential amplifier includes a current source and paired transistors. The paired transistors generate an output signal by dividing a source current supplied by the current source into emitter currents of the paired transistors in response to a difference between an input signal and a reference signal. A compensator includes an amplifying transistor and a feedback circuit that feeds a collector current output from a collector of the amplifying transistor back to a base of the amplifying transistor therethrough. The compensator generates the reference signal at a base of the amplifying transistor. The compensator decreases power consumption of the amplifying transistor when the collector current increases, and increases the power consumption of the amplifying transistor when the collector current decreases. The compensator suppresses a peaking of gain in a low frequency band. | ||||||
| 78 | METHOD AND SYSTEM FOR PROVIDING AUTOMATIC GATE BIAS AND BIAS SEQUENCING FOR FIELD EFFECT TRANSISTORS | US14626580 | 2015-02-19 | US20170093353A1 | 2017-03-30 | Lloyd L. Lautzenhiser |
| A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices. | ||||||
| 79 | MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING | US15207362 | 2016-07-11 | US20160320781A1 | 2016-11-03 | David M. SIGNOFF; Ming HE; Wayne A. LOEB |
| A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. | ||||||
| 80 | CONSTANT TRANSCONDUCTANCE BIAS CIRCUIT | US15202193 | 2016-07-05 | US20160315593A1 | 2016-10-27 | Yu-Jiu Wang; Ching-Yun CHU |
| A bias circuit is adapted for biasing a to-be-biased transconductance cell such that the to-be-biased transconductance cell has a constant transconductance, and includes a converter and a controller. The converter receives first and second current signals, and generates, based on the first and second current signals, a first voltage signal, a second voltage signal and a bias voltage that is for biasing the to-be-biased transconductance cell. The controller receives the first and second voltage signals from the converter, generates the first and second current signals for the converter based on the first and second voltage signals so as to make a magnitude of the first voltage signal equal a magnitude of the second voltage signal. | ||||||
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