Special masking method of fabricating a planar avalanche transistor专利检索-雪崩击穿微电子学专利检索查询-专利查询网

Special masking method of fabricating a planar avalanche transistor

阅读：790发布：2021-08-12

专利汇可以提供Special masking method of fabricating a planar avalanche transistor专利检索，专利查询，专利分析的服务。并且An avalanche junction transistor is fabricated by growing on an n+-type substrate an n-type epitaxial layer, masking all but a central region of the epitaxial layer, converting the central region of the epitaxial layer to p-type material, substantially increasing the diameter of the aperture in the mask and converting a portion of the p-type material to n+-type material. Connections are provided to the central n+-type region and the ntype epitaxial layer. Accordingly, the surface portion of the resulting p-n+ junction is located in a region of relatively low impurity concentration; consequently, avalanche breakdown is restricted to a region below the surface of the junction, thereby avoiding surface breakdown that would otherwise degrade transistor performance.，下面是Special masking method of fabricating a planar avalanche transistor专利的具体信息内容。

权利要求

2. A process for producing an avalanche junction in a semiconductor device comprising the steps of: forming on a low resistivity substrate of semiconductor material of one conductivity type a relatively high resistivity epitaxial layer of the same conductivity type; forming over the epitaxial layer a masking layer; forming an aperture in the masking layer, whereby a region of the epitaxial layer is exposed; diffusing a first impurity through the aperture into the exposed epitaxial layer, whereby a first diffusion region of opposite conductivity of the original epitaxial layer is formed to a depth of the original substrate; substantially increasing the lateral extent of the aperture in the masking layer by an effective amount to decrease the surface impurity concentration of a p-n junction formed by the diffusion of a second impurity through tHe aperture in the oxide mask, such that avalanche breakdown of the p-n junction occurs below the planar surface and does not degrade transistor performance; and diffusing an impurity through the increased aperture, whereby a second diffusion region of the same conductivity type as the substrate is formed.

3. A method for producing an avalanche junction in a semiconductor device comprising the steps of: forming a relatively low resistivity substrate of semiconductor material of one conductivity type a relatively high resistivity epitaxial layer of the same conductivity type; forming over the epitaxial layer a masking layer; forming a first aperture in the masking layer, whereby a first region of the epitaxial layer is exposed; diffusing an impurity through the entire first aperture into the first exposed epitaxial region, whereby a first diffused region is formed that extends to a depth of the substrate and is of opposite conductivity of the epitaxial layer; substantially increasing the lateral extent of the first aperture by an effective amount to decrease the surface impurity concentration of a p-n junction formed by the diffusion of the second impurity through the aperture in the mask, such that avalanche breakdown of the p-n junction occurs below the planar surface and does not degrade transistor performance; forming a second aperture in the masking layer, whereby a region of the epitaxial layer other than the first diffused region is exposed; diffusing an impurity into the entire areas of the two apertures, whereby a second diffusion of opposite conductivity to the first diffusion region is formed within the first diffusion region and the epitaxial region below the second aperture is converted from relative high resistivity material to relatively low resistivity material; and making separate transparent connections to both of the exposed regions of the epitaxial layer.

4. A method for producing an avalanche junction in a planar semiconductor device comprising the steps of: masking all but a central portion of a sample of semiconductive material of one conductivity type; diffusing into the central portion of the semiconductor material a first impurity that converts the conductivity type of the diffused region; substantially increasing the lateral extent of the exposed central portion of the semiconductive layer by an effective amount to decrease the surface impurity concentration of a p-n junction formed by the diffusion of a second impurity into the central portion of the semiconductive material such that avalanche breakdown of the p-n junction occurs below the planar surface; and diffusing into the increased central portion of the semiconductive material a second impurity that converts the conductivity type of a region within the diffused region.

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Special masking method of fabricating a planar avalanche transistor

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