ENERGY-EFFICIENT DUAL-RAIL KEEPERLESS DOMINO DATAPATH CIRCUITS
专利汇可以提供ENERGY-EFFICIENT DUAL-RAIL KEEPERLESS DOMINO DATAPATH CIRCUITS专利检索，专利查询，专利分析的服务。并且Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry, and/or have cross-coupled keeper circuitry to eliminate/reduce keeper contention during domino logic evaluation. The apparatus may comprise second clocked transistors having gates coupled to the clock signal path, first terminals coupled to one or more second junction nodes, and second terminals coupled to a second power rail. The apparatus may comprise sets of evaluation transistors having conducting channels coupled in series, coupled to the one or more first junction nodes, and coupled to one of the one or more second junction nodes. A NAND or inverter circuitry with inputs is coupled to the one or more first junction nodes.，下面是ENERGY-EFFICIENT DUAL-RAIL KEEPERLESS DOMINO DATAPATH CIRCUITS专利的具体信息内容。
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