Transistor comprising layers of silicon dioxide and silicon nitride
阅读：634发布：2023-05-01
专利汇可以提供Transistor comprising layers of silicon dioxide and silicon nitride专利检索，专利查询，专利分析的服务。并且A semiconductor structure in which a substrate having surface regions of opposite type conductivity is covered with two different insulating layers. In a specific structure, the regions in the substrate form an isolated gate field effect transistor with a thin layer of silicon nitride forming the insulation in the gate portion and a thicker layer of silicon dioxide forming the insulation over the remainder of the device.，下面是Transistor comprising layers of silicon dioxide and silicon nitride专利的具体信息内容。
2. A field effect transistor comprising, in combination a monocrystalline semiconductor substrate of one type conductivity having formed therein two spaced regions of another type conductivity, each extending from one surface of said substrate; a first insulating layer comprising a composite of a lower layer of silicon dioxide and an upper layer of silicon nitride covering said surface between said two spaced regions; a second insulating layer comprising a silicon dioxide layer having a greater thickness than said first layer covering portions of said surface not covered by said first insulating layer; a gate electrode located on said silicon nitride layer; ohmic contacts to each of said two regions respectively to provide source and drain connections; a current carrying conductive metal land pattern located on said gate and said second insulating layer and connected respectively to said gate electrode and said ohmic contacts thereby providing a high capacitive effect on the portion of said semiconductor substrate located beneath said first insulating layer and a low capacitive effect on the portion of said semiconductor substrate located beneath said second insulating layer.
3. The field effect transistor of claim 2 wherein said second insulating layer consists of a silicon dioxide layer and covers said two spaced regions, and said land pattern connected to said ohmic contacts is on the surface of said silicon dioxide layer.
4. The field effect transistor of claim 3 wherein said substrate is of P-type conductivity and said spaced regions are of N-type conductivity.
5. The field effect transistor of claim 3 wherein said substrate is of N-type conductivity and said spaced regions are of P-type conductivity.
6. A semiconductor device comprising, in combination, a monocrystalline semiconductor substrate having two regions of N-type conductivity provided in a semiconductor body of opposite type conductivity; ohmic contact to each of said two regions providing source and drain connections, respectively; two different insulating layers located on a surface of said substrate, one of said insulating layers consisting of silicon nitride and having a smaller thickness than the other insulating layer consisting of silicon dioxide; a thin silicon dioxide layer located on the surface of said semiconductor body between said tow N-type regions thereby forming an N-type inverted channel along the semiconductor surface between said two regions of N-type conductivity, said silicon nitride layer being located on said thin silicon dioxide layer; a gate electrode located on the surface of said silicon nitride layer and a current carrying conductive metal land pattern located on a surface portion of said silicon dioxide insulating layer; thereby providing a low capacitive effect on the portion of said semiconductor substrate located beneath said silicon dioxide insulating layer and a high capacitive effect on the portion of the semiconductor substrate located beneath said silicon nitride layer.
7. A semiconductor device comprising, in combination, a monocrystalline semiconductor substrate having regions of opposite type conductivity; two different insulating layers located on a surface of said substrate, one of said insulating layers consisting of silicon nitride and having a smaller thickness than the other insulating layer consisting of silicon dioxide; said substrate comprising emitter, base and collector regions of a transistor device, said silicon nitride layer being located on the semiconductor surface at the surface region of the base-collector junction of the transistor; and a current carrying conductive metal land pattern located on a surface portion of each of said two insulating layers thereby providing a high capacitive effect on the portion of said semiconductor substrate located beneath said silicon nitride layer and a low capacitive effect on the portion of said semiconductor substrate located beneath said other insulating layer.
8. A semiconductor device in accordance with claim 7 wherein said silicon nitride layer has a substantially annular configuration.
9. A semiconductor device comprising, in combination, a monocrystalline semiconductor substrate having regions of opposite type conductivity; two different insulating layers located on a surface of said substrate, one of said insulating layers consisting of silicon nitride and having a smaller thickness than the other insulating layer consisting of silicon dioxide; said substrate comprising emitter, base and collector regions of a transistor device, said silicon nitride layer having a substantially annular configuration and located on the surface of a P-type region to prevent the formation of an N-type inversion channel across the P-type surface region; and a current carrying conductive metal land pattern located on a surface portion of each of said two insulating layers thereby providing a high capacitive effect on the portion of said semiconductor substrate located beneath said silicon nitride layer and a low capacitive effect on the portion of said semiconductor substrate located beneath said other insulating layer.
10. A semiconductor device comprising, in combination, a monocrystalline semiconductor substrate having regions of opposite type conductivity; two different insulating layers located on a surface of said substrate, one of said insulating layers consisting of silicon nitride and having a smaller thickness than the other insulating layer consisting of silicon dioxide; said substrate comprising emitter, base and collector regions of a transistor device; and a current carrying conductive metal land pattern located on a surface portion of each of said two insulating layers thereby providing a high capacitive effect on the portion of said semiconductor substrate located beneath said silicon nitride layer and a low capacitive effect on the portion of said semiconductor substrate located beneath the other insulating layer, said land pattern including a metal base ohmic contact having a substantially annular extended portion located on a surface portion of said silicon dioxide layer, and a substantially annular metal portion extending from said annular extended portion and located adjacent to the base-collector junction of said transistor device; said silicon nitride layer having a substantially annular configuration and located between said substantially annular metal portion and the surface region of said base-collector junction.
11. A semiconductor device comprising, in combination, a monocrystalline semiconductor substrate having regions of opposite type conductivity; two dIfferent insulating layers located on a surface of said substrate, one of said insulating layers consisting of silicon nitride and having a smaller thickness than the other insulating layer consisting of silicon dioxide, said silicon nitride layer being located above a semiconductor region of one type conductivity; and a current carrying conductive metal land pattern located on a surface portion of each of said two insulating layers thereby providing a high capacitive effect on the portion of said semiconductor substrate located beneath said silicon nitride layer and a low capacitive effect on the portion of said semiconductor substrate located beneath the other insulating layer; said land pattern including a first current carrying electrode located on a surface portion of said silicon dioxide layer, said first current carrying electrode extending over a surface portion of said silicon nitride layer and having a portion in ohmic contact with the semiconductor region of said one type conductivity; and a second current carrying electrode extending over a surface portion of said silicon dioxide layer and forming an ohmic contact through an opening in said silicon dioxide layer to the semiconductor region of said one type conductivity.
12. A semiconductor device comprising, in combination, a monocrystalline semiconductor substrate having two regions of P-type conductivity provided in a semiconductor body of opposite type conductivity; ohmic contact to each of said two regions providing source and drain connections, respectively; two different insulating layers located on a surface of said substrate, one of said insulating layers consisting of silicon nitride and having a smaller thickness than the other insulating layer consisting of silicon dioxide; a thin silicon dioxide layer located on the surface of said semiconductor body between said two P-type regions thereby forming a P-type inverted channel along the semiconductor surface between said two regions of P-type conductivity, said silicon nitride layer being located on said thin silicon dioxide layer; a gate electrode located on the surface of said silicon nitride layer; and a current carrying conductive metal land pattern located on a surface portion of said silicon dioxide insulating thereby providing a low capacitive effect on the portion of said semiconductor substrate located beneath said silicon dioxide insulating layer and a high capacitive effect on the portion of the semiconductor substrate located beneath said silicon nitride layer.
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