专利汇可以提供Method of Manufacturing Trenched Mosfets with Embedded Schottky in the Same Cell专利检索,专利查询,专利分析的服务。并且A method for manufacturing a trenched semiconductor power device includes a step of forming said semiconductor power device with a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The method further includes the steps of covering the MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through the source and body regions into an epitaxial layer underneath for filling a contact metal plug therein. And, the method further includes a step of forming an embedded Schottky diode by forming a Schottky barrier layer near a bottom of the source-body contact trench below the contact metal plug with the Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source.,下面是Method of Manufacturing Trenched Mosfets with Embedded Schottky in the Same Cell专利的具体信息内容。
I claim:
This Patent Application is a Divisional Application and claims the Priority Date of a co-pending application Ser. No. 11/732,955 filed on Apr. 4, 2007 by common Inventors of this Application. The Disclosures made in the patent application Ser. No. 11/732,955 are hereby incorporated by reference.
1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell configuration and processes to manufacture MOSFET device with embedded Schottky diodes in the same cell such that integrated cells with spacing savings and lower capacitance and higher performance are achieved.
2. Description of the Related Art
Conventional technologies for high efficiency DC/DC applications, a Schottky diode are usually added externally in parallel to a semiconductor power device, e.g., a power MOSFET device.
In U.S. Pat. No. 6,433,396, a trench MOSFET device with a planar Schottky diode is disclosed as that shown in
In U.S. Pat. No. 6,998,678 discloses another trench semiconductor arrangement as shown in
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for design and fabrication of the trenched power device, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to provide more integrated semiconductor power devices with embedded Schottky diode that can accomplish space saving and capacitance reduction such that the above discussed technical limitations can be resolved.
It is therefore an aspect of the present invention to provide new and improved semiconductor power device configuration and manufacture processes for providing semiconductor power devices with embedded Schottky diode such that space occupied by separate Schottky diodes can be saved and one of the major technical limitations discussed above can be overcome.
Another aspect of the present invention is to provide new and improved semiconductor power device configuration and manufacture processes for providing semiconductor power devices with embedded Schottky diode in the same cell such that parasitic capacitance can be reduced and device performance can be improved.
Another aspect of the present invention is to provide new and improved semiconductor power device configuration and manufacture processes for providing semiconductor power devices with embedded Schottky diode in the same cell wherein the manufacturing processes can be simplified with reduced number of masks required such that the production costs can be reduced and reliability of the products can be enhanced.
Another aspect of the present invention is to provide new and improved semiconductor power device configuration and manufacture processes for providing semiconductor power devices with embedded Schottky diode in the same cell wherein a dopant regions is provided at the bottom of a contact trench below the Schottky layer to reduce the forward voltage of the Schottky diodes such that improved device performance is achieved.
Another aspect of the present invention is to provide new and improved semiconductor power device configuration and manufacture processes for providing semiconductor power devices with embedded Schottky diode in the same cell wherein a dopant regions is provided at the bottom of a contact trench below the Schottky layer to reduce the ldsx is reduced and device performance improvements are achieved.
Briefly, in a preferred embodiment, the present invention discloses a semiconductor power device comprising trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an insulation layer covering the trenched semiconductor power device with a source-body contact trench opened therethrough and further through the body regions into an epitaxial layer underneath and filled with contact metal plug therein. The semiconductor power device further includes an embedded Schottky diode disposed near a bottom of the source-body contact trench below the contact metal plug wherein the Schottky diode further includes a Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source. In an exemplary embodiment, the semiconductor power device further includes a contact enhancement dopant region disposed along a sidewall of the source-body contact trench for improving an electrical contact of the contact metal plug to the source and body regions. In an exemplary embodiment, the embedded Schottky diode further includes a CoSi2/TiN barrier layer disposed below the contact metal plug. In an exemplary embodiment, the metal contact plug further includes a tungsten plug filling in the source-body contact trench for contacting the body regions. In an exemplary embodiment, the a contact enhancement dopant region disposed along a side wall of the source-body contact trench further includes a P-type body-dopant region for improving an electrical contact of the contact metal plug to the body regions. In an exemplary embodiment, the embedded Schottky diode further includes a PtSi barrier layer disposed below the contact metal plug. In an exemplary embodiment, the embedded Schottky diode further includes a barrier layer having a barrier height larger than a leakage prevention voltage for preventing a leakage current during a reverse bias between the drain and the source and the barrier layer having a forward voltage drop less than a parasitic body diode between the body region and an epitaxial layer surrounding the body region. In an exemplary embodiment, the contact metal plug further includes a Ti/TiN barrier layer surrounding a tungsten core as a source-body contact metal. In an exemplary embodiment, the semiconductor power device further includes a thin resistance-reduction conductive layer disposed on a top surface covering the insulation layer and contacting the contact metal plug whereby the resistance-reduction conductive layer having a greater area than a top surface of the contact metal plug for reducing a source-body resistance. In an exemplary embodiment, the semiconductor power device further includes a thin resistance-reduction conductive layer includes a Ti or Ti/TiN layer disposed on a top surface covering the insulation layer and contacting the contact metal plug whereby the resistance-reduction conductive layer having a greater area than a top surface of the contact metal plug for reducing a source-body resistance. In an exemplary embodiment, the semiconductor power device further includes a thick front metal layer disposed on top of the resistance-reduction layer for providing a make contact with layer for a wire or wireless bonding package. In an exemplary embodiment, the semiconductor power device further includes a trenched MOSFET device. In an exemplary embodiment, the semiconductor power device further includes a source-dopant region disposed below the source-body contact trench in contact with the barrier layer of the Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of an epitaxial layer surrounding the body region supported on the semiconductor substrate. In an exemplary embodiment, the semiconductor power device further includes a source-dopant region disposed below the source-body contact trench in contact with the barrier layer of the Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of an epitaxial layer surrounding the body region supported on the semiconductor substrate. In an exemplary embodiment, the trenched gate is filled with a dielectric material padded by a gate oxide layer with a bottom gate oxide layer significantly thicker than the gate oxide layer disposed along sidewalls of the trenched gate.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.
Please refer to
The MOSFET device with embedded Schottky diodes have the advantages that the Schottky diodes are provided with less space occupied by the Schottky diodes because the diodes are formed as part of the trench contacts in the same area as part of the cells of the MOSFET power device. Compared to the patented inventions disclosed above, the space saving is at least 50%. The source contact with either N+ or P+ regions, i.e., dopant regions 140 are formed on the sidewalls of the trench contact and the Schottky diodes formed on the bottom of the trench contact achieve process savings because there is no requirement of P+ mask when compared with the device as that disclosed in U.S. Pat. No. 6,998,678. Furthermore, since the MOSFET and the Schottky diodes share the same trenches, there is less parasitic capacitance thus providing devices capable of providing higher performance with higher switching speed.
Besides optimizing trench contact CD and depth, and the Schottky barrier layer 145 to target Vf, there is another alternative method to further improve Vf by ion implantation of 1st conductivity dopant into trench bottom.
Referring to
In
According to the above drawings and descriptions, this invention further discloses a method for manufacturing a trenched semiconductor power device includes a step of covering the MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through the source and body regions and into an epitaxial layer below the body region for filling a contact metal plug therein. The method further includes a step of forming an embedded Schottky diode by forming a Schottky barrier layer along sidewall of the source-body contact trench in the epitaxial layer and near a bottom of the source-body contact trench below the contact metal plug with the Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source. The method further includes a step of forming a source-dopant region below the source-body contact trench in contact with the Schottky barrier layer of the Schottky diode having a different dopant concentration from the epitaxial layer surrounding the body region supported on the semiconductor substrate. In an embodiment, the method further includes a step of forming a contact enhancement dopant region along sidewalls of the source-body contact trench for improving an electrical contact of the contact metal plug to the body regions. In another embodiment, the step of forming the embedded Schottky diode further comprises a step of forming a CoSi2/TiN barrier layer at a bottom surface of the source-body contact trench. In another embodiment, the step of forming the embedded Schottky diode further comprises a step of forming a PtSi barrier layer at a bottom surface of the source-body contact trench. In another embodiment, the method further includes a step of forming the source-dopant region below the source-body contact trench in contact with the barrier layer of the Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of an epitaxial layer surrounding the body region supported on the semiconductor substrate. In another embodiment, the method further includes a step of forming the source-dopant region below the source-body contact trench in contact with the barrier layer of the Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of an epitaxial layer surrounding the body region supported on the semiconductor substrate. In another embodiment, the method further includes a step of forming the source-dopant region below the source-body contact trench in contact with the barrier layer of the Schottky diode having a dopant concentration of N2 with N2>N1 where N1 is a dopant concentration of an epitaxial layer surrounding the body region supported on the semiconductor substrate. The method further includes a step of forming a gate insulation layer padded on sidewalls and a bottom surface of the trenched gate and filling the trenched gate with a dielectric material by with the gate insulation layer on the bottom surface of the trenched gate significantly thicker than the gate insulation layer disposed along sidewalls of the trenched gate. In another embodiment, the method further includes a step of forming a gate insulation layer padded on sidewalls and a bottom surface of the trenched gate and filling the trenched gate with a dielectric material by with the gate insulation layer on the bottom surface of the trenched gate substantially same as the gate insulation layer disposed along sidewalls of the trenched gate. In another embodiment, the method further includes a step of forming a source-dopant region below the source-body contact trench in contact with the barrier layer of the Schottky diode having a dopant concentration of N2 with N2<N1 to reduce a Drain-Source leakage current at a reverse bias where N1 is a dopant concentration of an epitaxial layer surrounding the body region supported on the semiconductor substrate. The method further includes a step of forming a gate insulation layer padded on sidewalls and a bottom surface of the trenched gate and filling the trenched gate with a dielectric material by with the gate insulation layer on the bottom surface of the trenched gate significantly thicker than the gate insulation layer disposed along sidewalls of the trenched gate.
Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
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