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Transistor recording circuit with commutator

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专利汇可以提供Transistor recording circuit with commutator专利检索,专利查询,专利分析的服务。并且An electronic multiplier for producing an algebraic product comprising means for selectively recording a series of positive dipoles and negative dipoles with blank zones on a mobile information memory track and a corresponding series of either positive or negative dipoles on a mobile reference memory track and means for simultaneously reading and converting to electrical signals successive dipoles (or zones) on the information track and successive dipoles on the reference track and for effecting the product of said signals, wherein the recording on the information memory track is effected by apparatus including a transistorized comparer connected with a transistorized commutator.,下面是Transistor recording circuit with commutator专利的具体信息内容。

1. A dynamic memory and reading system of the type embodying writing heads and reading heads each outfitted with an electric winding, magnetic-layered or coated mobile component where signals may be recorded on and read from a data or information track and a reference track by applying electrical voltages to the writing head windings and by collecting electrical voltages on the reading head windings, the information (or data) track presenting positive dipoles, negative dipoles and demagnetized zones, and the reference track presenting dipoles all of the same sign, said dipoles and zones on the information track being so spaced thereon that each may be read by a reading head simultaneously with the reading of a dipole on the reference track by a reading head, and means for effecting the product of the electrical voltages simultaneously collected on a reading head winding from the information track and on a reading head winding from the reference track.
2. Apparatus for the recording of signals on a magnetic memory track comprising a two-input-electrode and two-output-electrode comparer, said comparer being capable of delivering on its two output electrodes positive and negative voltages if one furnishes to a said input electrode positive, negative and valueless (0) voltages, and to the other input electrode a valueless (0) voltage, and a commutator embodying an output terminal connected to a writing head winding, a control terminal joined to an output electrode of the comparer, a first input terminal joined to the other output terminal of the comparer, and a second input terminal receiving high-frequency alternating current voltage of mean 0 value, said commutator being capable of connecting its output terminal to said first input terminal whenever its control terminal is supplied with a voltage of a predetermined sign, and capable of connecting its output terminal to its second input terminal whenever its control terminal is supplied with a voltage of the contrary sign.
3. Apparatus according to claim 2 wherein the high-frequency voltage applied to said second input terminal of the commutator has a frequency of about 100 kilocycles.
4. Apparatus according to claim 2 wherein the commutator comprises two inverse-type transistors embodying emitters, collectors and bases, said bases being connected to each other and with the control terminal of the commutator with the aid of equal resistances, the emitter of one transistor and the collector of the other transistor being connected to each other and to the output terminal of the commutator.
5. Apparatus according to claim 2 wherein the comparer comprises two primary transistors of the same type having emitters, collectors and bases, the base of each being coupled to the emitter of the other and to an input electrode of the comparer, two secondary transistors of types identical to each other, having emitters coupled to each other, collectors coupled to one common point through the intermediary of resistances and of which one is connected to an output electrode of the comparer, and bases coupled to the colLectors of the two primary transistors, and a final transistor of a type identical to the secondary transistors having its emitter and its collector coupled respectively to the emitters and collectors of said secondary transistors, the base of said final transistor being connected to the collectors of said secondary transistors and to a source of voltage through resistances.
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