Address translation logic which permits a monolithic memory to utilize defective storage cells专利检索-翻译记忆翻译管理系统人工智能专利检索查询-专利查询网

Address translation logic which permits a monolithic memory to utilize defective storage cells

阅读：312发布：2021-01-08

专利汇可以提供Address translation logic which permits a monolithic memory to utilize defective storage cells专利检索，专利查询，专利分析的服务。并且In the production of monolithic memory chips used in computer storage devices a certain percentage is rejected in production as containing one or more defective bit cells on the chip. These almost perfect chips are arranged on a memory card bit so that all of the bit cards of a particular memory product are identical to those sections containing defective bit cells. The valid cells are logically arranged in contiguous address locations by translation logic which converts the address before it is presented to the memory bit cards. Addresses presented to the logic are re-ordered such that all addresses that, untranslated, would have selected a defective area of a chip, after being translated select a non-defective area of a chip.，下面是Address translation logic which permits a monolithic memory to utilize defective storage cells专利的具体信息内容。

权利要求

1. For use in a memory system of the type in which a plurality of addressable locations are selected by decoding means which decode a cOntiguous set of unique first address manifestations, a translator for translating said first address manifestation into a set of unique second address manifestations which omit predetermined ones of said contiguous set comprising: a number (n-k) of input leads each representing a bit position order of said first address manifestations; a number (m) of output leads each representing a bit position of said second address manifestations and having a one-for-one correspondence with said first input leads; means connecting each of k input leads to the next higher order output lead; and means connecting at least one of said k input leads to two or more of said output leads; whereby said decoder translates n of the address bits comprising said first address manifestations into m address bits of said second address manifestations wherein one of said n bits controls at least two of said m bits.

2. The combination according to claim 1 wherein the input lead representing the highest order bit position of said first address manifestation is exclusive ORed with said means connecting said one of said k input leads to said two of said output leads.

说明书全文

相关专利内容

标题	发布/更新时间	阅读量
抗TREM2抗体和其使用方法	2020-05-13	936
一种包含人工智能的人机结合译文批量处理翻译方法	2020-05-11	162
一种手指皮纹关联多元智能特征的检测方法	2020-05-14	972
人工智能CNN、LSTM神经网络语音识别系统	2020-05-12	751
一种燕窝胶原蛋白肽饮品	2020-05-14	335
一种打印方法以及无字库打印机	2020-05-15	666
采用隐树注意力的神经机器翻译	2020-05-14	589
一种用于英语翻译的教学板	2020-05-08	450
一种配合平板电脑翻译的阅读适配尺	2020-05-12	866
一种用于英语教学的教学设备	2020-05-14	26

高效检索全球专利

专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台，是提供专利分析，专利查询，专利检索等数据服务功能的知识产权数据服务商。

我们的产品包含105个国家的1.26亿组数据，免费查、免费专利分析。

申请试用

分析报告

专利汇分析报告产品可以对行业情报数据进行梳理分析，涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度，系统通过AI智能系统对图表进行解读，只需1分钟，一键生成行业专利分析报告。

申请试用

翻译记忆热门专利

热门分类

Address translation logic which permits a monolithic memory to utilize defective storage cells

该功能需要专业版企业版VIP权限，您可以：