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多晶片封裝鏈結技術

阅读:1038发布:2020-10-04

专利汇可以提供多晶片封裝鏈結技術专利检索,专利查询,专利分析的服务。并且諸如邏輯PHY之系統單晶片可被分成具有固定路由之硬IP區塊及具有靈活路由之軟IP區塊。每一硬IP區塊可提供固定數目個線道。使用
p 個硬IP區塊,其中每一區塊提供
n 個資料線道,提供
h =
n *
p 個總硬IP資料線道。在系統設計需要
k 個總資料線道的情況下,可能
k ≠
h ,使得

k /
n

個硬IP區塊提供 h = n * p 個可利用的硬IP資料線道。 Each hard IP block provides h = n * p available hard IP data channels.
在該狀況下, h - k 個道可禁用。 In this situation, h - k channels can be disabled.
在諸如硬IP與軟IP之間的道倒轉發生的狀況下,可藉由軟IP內之多工器類可規劃切換器之使用避免蝶形路由。 In situations such as the occurrence of channel reversal between hard IP and soft IP, the use of programmable switches in the soft IP can be used to avoid butterfly routing.
A system single chip such as a logical PHY can be divided into hard IP blocks with fixed routing and soft IP blocks with flexible routing. Each hard IP block can provide a fixed number of lanes. Use p hard IP blocks, each of which provides n data lanes, providing h = n * p total hard IP data lanes. In the case where the system design requires k total data lines, it may be k ≠ h , making A system single chip such as a logical PHY can be divided into hard IP blocks with fixed routing and soft IP blocks with flexible routing. Each hard IP block can provide a fixed number of lanes. Use p hard IP blocks, each of which provides n data lanes, providing h = n * p total hard IP data lanes. In the case where the system design requires k total data lines, it may be k ≠ h , making

k / n k / n

The hard IP blocks provide h = n * p available hard IP data lanes. In this case, h - k tracks can be disabled. In the event that a path reversal, such as between hard IP and soft IP, occurs, the butterfly routing can be avoided by the use of a multiplexer class within the soft IP planable switch. The hard IP blocks provide h = n * p available hard IP data lanes. In this case, h - k tracks can be disabled. In the event that a path reversal, such as between hard IP and soft IP, occurs, the butterfly routing can be avoided by the use of a multiplexer class within the soft IP planable switch.,下面是多晶片封裝鏈結技術专利的具体信息内容。

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