Stochastic A/D converter and method for using the same |
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申请号 | EP11173743.3 | 申请日 | 2011-07-13 | 公开(公告)号 | EP2546992B1 | 公开(公告)日 | 2014-03-05 |
申请人 | IMEC; | 发明人 | Verbruggen, Bob; Craninckx, Jan; | ||||
摘要 | |||||||
权利要求 | |||||||
说明书全文 | The present invention generally relates to analog to digital (A/D) conversion and more specifically to the design of an analog to digital converter with high accuracy and low power consumption. Analog-to-digital converters (ADCs) are an important part of many electronic systems. Their power consumption for a given resolution and speed has been improved significantly in recent years due to optimized architectures, novel circuit techniques and technology scaling. A/D converters contain circuits called comparators that each convert an analog signal into a one bit digital signal. In most efficient ADC implementations these comparators are clocked and use regeneration to amplify small voltage differences to digital signal levels. The most important non-ideality they have to cope with when performing this task, is the comparator noise. Comparator noise is a well-known impairment which potentially degrades the performance of most conventional ADCs. Due to this noise the comparator may output a wrong decision, i.e. the comparator outputs a zero instead of a one or vice versa. In most ADC architectures these decision errors degrade the overall conversion result, thereby decreasing the signal-to-noise ratio (SNR) and hence the Effective Number of Bits (ENOB). The obvious solution to this problem is to simply decrease the probability that the comparator make a wrong decision. However, for a given comparator topology reducing the error probability inevitably results in increased power consumption, reduced bandwidth or reduced speed. This approach therefore degrades the other ADC performance metrics since an extra bit of resolution requires a factor 4 increase in comparator power. An alternative approach is to use an ADC architecture that is more robust to comparator errors, such as pipeline. Another alternative, which is nowadays seen as the most efficient converter implementation, employs redundant SAR (Successive Approximation Registers) converters. These alternatives typically feedback the potentially erroneous comparator decision and keep track of the residue. This residue can then either be amplified until the input referred comparator noise is no longer critical (pipeline converters) or be quantized at a later time with more accurate comparators. The effect of comparator noise on a conventional ADC can be described more in detail as follows. The core function of an N-bit conventional ADC is to determine in which of 2N bins (digital values) defined by the N bits, the input voltage is located. This is done by comparing the input signal, either directly or indirectly, to a set of thresholds separating these bins. Simply put, the ADC has to find two adjacent thresholds such that the input is smaller than one and larger than the other. One obvious way of performing this search is in parallel, as in a flash ADC, with the equally obvious disadvantage that a large (2N - 1) number of comparisons is needed. By using a binary search, as in a SAR ADC, the number of comparisons can be reduced to just N. Many intermediate searching strategies are possible, but all of them share the need to compare the input signal or a signal derived thereof to a set of thresholds. Due to comparator noise, any of these comparisons can be in error, with highest probability of error when the threshold is close to the input. For simplicity, it is for now assumed that the comparator always returns the correct output if the difference between the input and the threshold is larger than half a bin width. Since the ADC does not know beforehand which thresholds are close to the input, all comparisons are potentially in error due to comparator noise. However, for any input of the ADC at most one comparison is noise-critical, since all other comparisons compare the input to a threshold which is at least half a bin width away. As already indicated, the conventional solution is to decrease the probability the comparator make a wrong decision, which however leads to the above-mentioned problems. As the increased power consumption in the comparator is not needed in any comparison but the noise-critical comparison, this is obviously very wasteful. Significant power savings would be possible if the ADC could somehow identify the critical comparison and use a lower-noise comparator when resolving it. Unfortunately, it is not possible to conclusively identify the critical comparison based on other comparisons. Indeed, even with a full set of noiseless comparators, one can only detect that the input is between two of these comparisons. While it can be asserted that one of the two is critical, there is no information at all to indicate which of the two is the critical one : at best one can therefore identify two potentially critical comparisons. The pair of potentially critical thresholds is identified at low power in the paper " The concept of combining a number of noisy comparator decisions is proposed in " Another related area is the work by Hence, there is a need for a low power analog-to-digital converter circuit that deals with comparator noise while using only the power consumption of a single noise-critical comparison. The present invention aims to provide a high accuracy, low power analog-to-digital converter circuit where the above-mentioned problems are overcome. The present invention relates to an analog-to-digital converter (ADC) circuit arranged for receiving an analog input signal and for outputting a digital representation of the analog input signal. The ADC circuit comprises :
The proposed circuit indeed overcomes the problems of the prior art solutions. In the first converter stage a digital representation of a certain bit length of the analog input signal is determined along with a residue signal representing the error made in this first stage. Then, in a second stage, a stochastic conversion is performed on the residue signal. A completion signal is generated when the operations in the first converter stage are terminated. This completion signal is fed to the second stage, more in particular to the clock generation circuit provided in that second stage. Reception of the completion signal initiates the operation of the second converter stage. The clock generation circuit generates a clock signal that activates the various comparators in the second stage. Each comparator receives the residual analog output signal and a common reference voltage to compare and a comparator decision is output. In the digital processing stage the comparator decisions are processed and a second set of conversion bits is produced. Due to the plurality of comparators and the decisions they produce, not only the sign but also the magnitude of the input signal can be estimated. The digital representation of the applied analog input signal is then obtained by combining the first and second set of conversion bits. In a preferred embodiment the second stage further comprises a counter that counts clock pulses and, when the number of clock pulses reaches a given value, generates a second completion signal for controlling the number of times the clock signal is generated. Preferably the A/D converter circuit of the invention further comprises a digital-to-analog converter circuit for generating the signal represented by the first set of conversion bits. In another preferred embodiment the A/D converter circuit further comprises subtraction means for generating the residual analog output signal. The digital processing stage comprised in the second converter stage is preferably arranged for determining an average value of the plurality of comparator decisions and for determining an input signal level corresponding to the average value. In a preferred embodiment the first converter stage is implemented as a successive approximation register analog-to-digital converter. Alternatively, the first converter stage can be implemented as a pipeline analog-to-digital converter comprising a plurality of pipelined stages, whereby said residual analog output signal is the residue signal of the last pipelined stage. In another aspect the invention relates to a method for converting an analog input signal into a digital representation of the analog input signal. The method comprises the steps of :
In a preferred embodiment a calibration step is performed for determining an indication of the comparator noise of the plurality of comparators.
The present invention discloses an analog-to-digital conversion (ADC) circuit based on the principle of a stochastic ADC. In the stochastic ADC according to the invention the comparator noise is not just tolerated : the proposed architecture leverages the inherent noise present in the comparator circuits to quantize an analog input signal. Whereas most conventional ADC architectures exhibit improved performance in the absence of comparator noise, the performance of the architecture according to this invention would degrade significantly without comparator noise, as will be explained below. The proposed ADC architecture comprises two conversion stages in order to increase the effective number of bits (ENOB) and lower the power consumption required for quantizing an analog input signal into its digital equivalent. The proposed architecture operates in two phases. First there is a conversion stage wherein a rough digital representation of the analog input signal is obtained, as well as an error signal. Next there is a stochastic conversion stage. Then the outcomes of the two stages are combined to produce the digital representation of the applied analog input signal. This is illustrated in The first conversion stage may for example be implemented as a Successive Approximation Register (SAR) A/D converter. A number of cycles of SAR operation generate a digital output word of a certain bit length and a residue voltage which represents the error made in this first conversion stage. The residue is then quantized in the second stochastic conversion stage. Finally, the results from the two phases are added to produce the final output. The first conversion stage can also be implemented as a pipeline A/D converter. This first stage then itself consists of a number of pipelined stages that each generate a digital output word of a certain bit length and a residue voltage which represents the error made in that stage. The residue voltage of the final pipeline stage can then be quantized in the second stochastic conversion stage. Finally, the digital results of the pipeline stages and the second stochastic stage are added to produce the final output. In general, the stochastic conversion stage can be applied in any ADC architecture where a small input signal (i.e. a signal of the order of magnitude of the comparator noise) must be quantized with high accuracy at low power. The proposed stochastic stage leverages comparator noise. This comparator noise can be accurately described by an equivalent Gaussian noise source which is added to the input signal. The sign of the sum of noise and input signal then determines the comparator output such that the probability of a positive comparator output depends on the input according to an error function, as shown in Conventionally, a comparator is designed to resolve a critical comparison in a given ADC, with requirements for decision time and r.m.s. noise derived from the overall ADC requirements for speed and signal-to-noise ratio (SNR). As shown in the background section, this comparator needs to take decisions at least twice in the prior art solutions, because of the inability to identify a single critical threshold. It is now shown how this factor two overhead can be avoided. In the present invention an architecture is proposed wherein the single comparator is physically split up in M smaller comparators, each with √M times higher r.m.s. noise but the same total power consumption. If these M low power comparators are then clocked, the average output converges to the probability corresponding to the applied input signal as shown in The advantage of the proposed approach is that by combining the results of the M noisy comparators, the system can estimate not only the sign of the input, as in a conventional comparator, but also the magnitude. Consequently, unlike in a conventional A/D converter, the comparisons do not need to be repeated for different, closely spaced thresholds, thus avoiding the factor two power waste in the power-critical comparison. It is important to note that in the absence of comparator noise, the M comparators return a same result, and no magnitude information can be gained. Comparator noise is therefore essential in the operation of the proposed stochastic stage. The flowchart of To accurately combine this second stage digital estimation with the digital output of the first stage, the two signals must be added with the correct coefficients. This can be achieved by multiplying the stochastic estimate with a digital signal representing the ratio of the r.m.s. comparator noise to the first stage least significant bit (LSB) and then adding the output of this multiplier to the first stage digital output. In practice the ratio of the r.m.s. comparator noise to the first stage LSB must be measured for example during an offline calibration by observing the average number of positive comparator outputs for two different, well-known inputs of the comparators. In the example of As an additional example, consider a stochastic conversion system with 64 comparisons calibrated using the method above to yield an estimated r.m.s. comparator noise of 1.19 LSB. If an input of -0.43 LSB is applied to this system, 20 of the 64 comparators might return a positive result, for an average output of 0.3125. As shown in Some details of an example implementation with a SAR first stage are discussed now. Reference is made to The most important choice for the stochastic ADC is the number of comparator decisions and their r.m.s. noise. For a constant comparator power in the second phase the number of comparators divided by the r.m.s. noise squared is constant. The effect of this trade-off is illustrated for 16 and 64 comparators with 0.5 mV and 1 mV r.m.s. comparator noise, respectively, in It is interesting to note that in Assume 64 comparator decisions with 1 mV r.m.s. noise are chosen. This choice limits the residue range the second phase can reliably quantize as shown in In this example another architectural choice is how these comparator decisions are obtained: in series by clocking a single comparator 64 times, in parallel by clocking 64 comparators once, or somewhere between these two extremes. The first option would obviously impose a serious speed penalty but would require the least hardware. The latter option is the fastest, but would require the most hardware, and also adds a significant amount of comparator input capacitance to the system. A compromise between input capacitance, complexity and speed should be found. The choice of how comparator decisions are obtained also affects the way comparator offset affects the second phase performance. In the "single-comparator" case, comparator offset is added as a fixed offset and not detrimental to performance as long as the useful range of the second phase is respected. If multiple comparators are used their individual offsets are essentially averaged and the overall effect is limited, as long as each comparator is still used in its "noisy" range. Although the present invention has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. In other words, it is contemplated to cover any and all modifications, variations or equivalents that fall within the scope of the basic underlying principles and whose essential attributes are claimed in this patent application. It will furthermore be understood by the reader of this patent application that the words "comprising" or "comprise" do not exclude other elements or steps, that the words "a" or "an" do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms "first", "second", third", "a", "b", "c", and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms "top", "bottom", "over", "under", and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention are capable of operating according to the present invention in other sequences, or in orientations different from the one(s) described or illustrated above. |