| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | Anaroguudejitaruhenkanki | JP6714375 | 1975-06-05 | JPS518858A | 1976-01-24 | ABURAHAMU FUUGENDOORUN; ROBERUTO EMIRU YOHAN FUAN DE G; TEODORASU YOSEFU FUAN KETSUSER |
| 42 | JPS4919931B1 - | JP4752670 | 1970-06-02 | JPS4919931B1 | 1974-05-21 | |
| 43 | Statistical estimation-based noise reduction technique for low power successive approximation register analog-to-digital converters | US15278519 | 2016-09-28 | US09774339B2 | 2017-09-26 | Nan Sun; Long Chen; Xiyuan Tang |
| Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being “1” or “0”. The estimation of a signal from a noisy environment using multiple trials can be cast as a classic statistical estimation issue. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC. | ||||||
| 44 | Analog-to-digital conversion | US15092416 | 2016-04-06 | US09660658B2 | 2017-05-23 | Robert Kolm; Christoph Boehm; Maximilian Hofer; Thomas Jackum; Stefan Schneider |
| At least one asymmetry element is configured to receive an input signal and is coupled to a first branch of a bi-stable flip-flop comprising the first branch and a second branch. An asymmetry between the first branch and the second branch depends on the input signal. A value indicative of the input signal is determined based on received output signals of a plurality of readout events. | ||||||
| 45 | STATISTICAL ESTIMATION-BASED NOISE REDUCTION TECHNIQUE FOR LOW POWER SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTERS | US15278519 | 2016-09-28 | US20170093414A1 | 2017-03-30 | Nan Sun; Long Chen; Xiyuan Tang |
| Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being “1” or “0”. The estimation of a signal from a noisy environment using multiple trials can be cast as a classic statistical estimation issue. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC. | ||||||
| 46 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM | US15238056 | 2016-08-16 | US20160365869A1 | 2016-12-15 | Raja Pullela; Curtis Ling |
| Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | ||||||
| 47 | ANALOG-TO-DIGITAL CONVERSION | US15092416 | 2016-04-06 | US20160308544A1 | 2016-10-20 | Robert Kolm; Christoph Boehm; Maximilian Hofer; Thomas Jackum; Stefan Schneider |
| At least one asymmetry element is configured to receive an input signal and is coupled to a first branch of a bi-stable flip-flop comprising the first branch and a second branch. An asymmetry between the first branch and the second branch depends on the input signal. A value indicative of the input signal is determined based on received output signals of a plurality of readout events. | ||||||
| 48 | Reconfigurable wideband channelized receiver | US14576039 | 2014-12-18 | US09197283B1 | 2015-11-24 | Tuan V. Nguyen; Oleg Brovko; Alison Kim; Jing Z. Stafsudd |
| A method and apparatus for sampling a high bandwidth analog signal includes: splitting the high bandwidth analog signal into N parallel channels; randomly demodulating each of the signals; sampling each demodulated signal using a sub-Nyquist sampling rate; combining each sampled signal into a sub-Nyquist signal; compressive sensing the combined sub-Nyquist signal to estimate missing samples of a full Nyquist rate uniform sample set X(n); convolving X(n) with N analysis filters, each analysis filter having a different coefficient; decimating output of each analysis filter using decimation ratios of M:1 to generate a sub-banded signal set Yi (n), i=1, . . . , N; processing the sub-banded signal set; up-sampling each processed sub-band signal by M; convolving each up-sampled sub-band signal with a corresponding synthesis filter; and combining two or more of the convolved signals to generate a non-uniform spectral partitioning of the high bandwidth analog signal. | ||||||
| 49 | Analog-to-digital converter | US13992112 | 2012-05-30 | US09083377B2 | 2015-07-14 | Hasnain Lakdawala; Ashoke Ravi; Degani Ofir; Alpman Erkan; Julia H. Lu; Gordon Eshel |
| A technique includes receiving an analog signal and generating at least one second signal that has a timing indicative of a magnitude of the analog signal. The technique includes acquiring a plurality of measurements of the timing, where the measurements vary according to a stochastic distribution; and providing a digital representation of the analog signal based at least in part on the measurements. | ||||||
| 50 | Stochastic encoding in analog to digital conversion | US14095690 | 2013-12-03 | US09077363B2 | 2015-07-07 | Thomas M. MacLeod |
| A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal. | ||||||
| 51 | Accuracy enhancement techniques for ADCs | US14043284 | 2013-10-01 | US09071261B2 | 2015-06-30 | Junhua Shen; Ronald A. Kapusta |
| Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error. | ||||||
| 52 | Spin torque transfer magnetic tunnel junction intelligent sensing | US13420890 | 2012-03-15 | US09053071B2 | 2015-06-09 | Abhishek Banerjee; Raghu Sagar Madala; Wenqing Wu; Kendrick H. Yuen; Chengzhi Pan |
| Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics. | ||||||
| 53 | ACCURACY ENHANCEMENT TECHNIQUES FOR ADCs | US14043284 | 2013-10-01 | US20150091744A1 | 2015-04-02 | Junhua SHEN; Ronald A. KAPUSTA |
| Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error. | ||||||
| 54 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM | US14558004 | 2014-12-02 | US20150084795A1 | 2015-03-26 | Raja Pullela; Curtis Ling |
| Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | ||||||
| 55 | Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm | US14248851 | 2014-04-09 | US08928506B2 | 2015-01-06 | Raja Pullela; Curtis Ling |
| Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. | ||||||
| 56 | SPIN TORQUE TRANSFER MAGNETIC TUNNEL JUNCTION INTELLIGENT SENSING | US13420890 | 2012-03-15 | US20130245999A1 | 2013-09-19 | Abhishek Banerjee; Raghu Sagar Madala; Wenqing Wu; Kendrick H. Yuen; Chengzhi Pan |
| Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics. | ||||||
| 57 | Stochastic analog-to-digital (A/D) converter and method for using the same | US13192056 | 2011-07-27 | US08384578B2 | 2013-02-26 | Bob Verbruggen; Jan Craninckx |
| An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes: a first converter stage configured for receiving the analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing the difference between the analog input signal and a signal represented by said first set of conversion bits, a second converter stage comprising a clock generation circuit arranged for receiving the first completion signal and for generating a clock signal, a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, a digital processing stage configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits. | ||||||
| 58 | Stochastic Analog-to-Digital (A/D) Converter And Method For Using The Same | US13192056 | 2011-07-27 | US20130015988A1 | 2013-01-17 | Bob Verbruggen; Jan Craninckx |
| An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes: a first converter stage configured for receiving the analog input signal and for generating a first set of conversion bits, a first completion signal and a residual analog output signal representing the difference between the analog input signal and a signal represented by said first set of conversion bits, a second converter stage comprising a clock generation circuit arranged for receiving the first completion signal and for generating a clock signal, a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, a digital processing stage configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits. | ||||||
| 59 | Digital-to-analog converter using pseudo-random sequences and a method for using the same | US10091032 | 2002-03-06 | US06617990B1 | 2003-09-09 | Eduardo Lorenzo-Luaces; Pertti O. Alapuranen; Guénaël T. Strutt |
| A system and method for providing discrete analog voltage levels. The system and method employs a pseudo-random sequence generator for generating random-sequences of binary values, namely zeros and ones, based on a digital input. The pseudo-random sequence serves to modulate a current source whose output is integrated to develop a constant discrete analog voltage output. This method reduces spurious frequency interference on the circuit. The system and method can be employed in a node of a wireless ad-hoc communications network. | ||||||
| 60 | Method of and system for generating digital test signals | US865501 | 1977-12-29 | US4161627A | 1979-07-17 | Bertram Amann |
| To test the performance of a PCM terminal operating in the TDM mode, a simulated message or noise signal is generated by extracting a recurrent sequence of code words from a read-only memory, the stored code words representing a set of values logarithmically related to sucdessive amplitudes of a sine wave or other periodic oscillation to be reproduced. These words are read out at a fixed scanning frequency f.sub.o but with skipping of (p-l) memory stages if a signal frequency pf.sub.o is to be simulated. A volume selector generates supplemental code words which are additively or subtractively combined with the extracted code words to simulate a desired voltage level. The resulting code words are compressed in a code converter in which the quantum steps of the segments of a compander characteristic, conforming to the chosen logarithmic function, are stored in another read-only memory. | ||||||
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