| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | Esd protection circuit | JP2008531442 | 2006-09-19 | JP4896137B2 | 2012-03-14 | インタット マ，; グアン−ピン リー， |
| 62 | Gain controlled low-noise amplifier means | JP2009511631 | 2007-05-15 | JP2009538552A | 2009-11-05 | アー イェー ベークマンズ エドウィン; ハー エム ヘセン レオナルドゥス |
| 利得制御式低雑音増幅手段を提供する。 この増幅手段は、増幅器（Ｔ１）と、この増幅器（Ｔ１）の入力端と出力端との間の増幅器（Ｔ１）の負帰還ループにおいて互いに逆方向で且つそれぞれ順方向で直列に結合されている第１及び第２のＰＩＮダイオード（Ｄ 1及びＤ 2 ）とを具えている。 この増幅手段は更に、第１のＰＩＮダイオードと第２のＰＩＮダイオードとの間のノードに結合されている第１の電流源（Ｉ C1 ）と、増幅器（Ｔ１）の入力端に接続されている第２の電流源（Ｉ C2 ）とを具えている。 | ||||||
| 63 | Zapping circuit | JP2006012141 | 2006-01-20 | JP2007194458A | 2007-08-02 | OTAKE SEIJI |
| PROBLEM TO BE SOLVED: To provide a zapping circuit capable of reducing the forming region of a driver element for zapping and reducing the area of an IC chip, by employing a resistance capable of being cut through melting by a low current and a low voltage. SOLUTION: In the zapping circuit, resistors 5-9 consisting of poly silicon film or tungsten silicon film are employed as a zapping element. MOS (metal oxide semiconductor) transistors 10-14 of low breakdown voltage are employed as a driver element for blowing out a part or the whole of resistors 5-9. In this case, the forming region of driver element for zapping can be contracted, and the area of IC chip can be reduced by employing the MOS transistors 10-14. COPYRIGHT: (C)2007,JPO&INPIT | ||||||
| 64 | Biased Darlington transistor pair, a method and system | JP2006542614 | 2004-11-17 | JP2007513574A | 2007-05-24 | グラス，ケビン; スミス，マルコム |
| 増幅器は、ダーリントン・トランジスタ対（１１０，１２０）および入力トランジスタ（１１０）中のバイアス電流を増加させるためのバイアスを与えるネットワークを含む。 回路（１００）は、入力トランジスタ（１１０）、第２トランジスタ（１２０）、無線周波数（ＲＦ）チョーク（１１２）、縮退インダクタ（１２２）、キャパシタ（１３２）および電圧制御電流源（１３０）を含む。 入力トランジスタ（１１０）および第２トランジスタ（１２０）は、コレクタがノード（１４２）でともに結合され、入力トランジスタ（１２０）のエミッタがノード（１１１）に結合されて、ダーリントン・トランジスタ対を形成するために結合される。 | ||||||
| 65 | 전력증폭기 | KR1020120052268 | 2012-05-17 | KR1020120134013A | 2012-12-11 | 오카무라아쓰시; 야마모토카즈야; 마쓰즈카타카유키 |
| PURPOSE: A power amplifier is provided to reduce bias currents according to a collector voltage which becomes lower than a predetermined threshold by including a bias current reduction circuit in a bias circuit. CONSTITUTION: An amplifier element comprises a base in which an input signal is input, a collector which is applied with a collector voltage, and an emitter. A bias circuit supplies bias currents to the base of the amplifier element. The bias circuit comprises a bias current reduction circuit(12) which reduces the bias currents according to the collector voltage which becomes lower than a predetermined threshold. The bias circuit includes a bias transistor, first resistance, and second resistance. The bias current reduction circuit includes a control terminal, a first terminal which is connected between and the first resistance and the second resistance, a transistor having an earthed second terminal, and a control circuit which supplies a control voltage to the control terminal in the transistor. [Reference numerals] (14) Control circuit | ||||||
| 66 | ＥＳＤ 보호회로 | KR1020087007232 | 2006-09-19 | KR1020080045244A | 2008-05-22 | 마인타트; 리구안핑 |
| Improved protection circuits are provided for use as voltage overload protection circuits, ESD protection circuits for RF input pins, and unit protection cells for distributed amplifiers. Preferably, the protection circuits include a positive threshold voltage trigger used to trigger a switch wherein the trigger includes a diode string in series with a resistor and the switch includes a bipolar transistor switch in series with a single reverse diode. Alternatively, the trigger includes a diode string in series with a single diode and a single resistor, and is used to trigger a Darlington pair transistor switch in series with a single reverse diode. In another embodiment, a Darlington pair transistor switch is triggered by a capacitor. In use with distributive amplifiers, the ESD protection circuits are preferably absorbed inside the artificial transmission lines of the distributed amplifier. | ||||||
| 67 | 증폭 장치, 증폭 시스템 및 증폭 방법 | KR1020067010732 | 2004-11-17 | KR100865544B1 | 2008-10-29 | 글라스케빈; 스미스말콤 |
| 증폭기는 다링톤 트랜지스터 쌍(110, 120)과 바이어스하는 네트워크를 포함하여 입력 트랜지스터(110)에서 바이어스 전류를 증가시킨다. 회로(100)는, 입력 트랜지스터(110), 제 2 트랜지스터(120), 무선 주파수(RF) 초크(112), 축퇴(degeneration) 인덕터(122), 커패시터(132), 및 전압 제어된 전류 소스(130)를 포함한다. 입력 트랜지스터(110) 및 제 2 트랜지스터(120)가 노드(142)에서 함께 연결된 콜렉터와 다링톤 트랜지스터 쌍을 형성하도록 연결되고, 그리고 입력 트랜지스터(110)의 에미터가 노드(111)에서 연결된다. | ||||||
| 68 | ZAPPING CIRCUIT | KR20070003740 | 2007-01-12 | KR20070077066A | 2007-07-25 | OTAKE SEIJI |
| A zapping circuit is provided to arbitrarily set a current value and a voltage value required for a zapping by controlling the length or width of a resistor. A switching circuit(1) is comprised of a power source circuit(2) for a zapping, a control circuit(3), a sensing circuit(4), resistors(5,6,7,8,9) for a zapping, and MOS transistors(10,11,12,13,14) for a driver. In case the resistors are formed through the same process applied to a gate electrode of each MOS transistor, a thickness of each transistor is constantly maintained and the respective resistors are arbitrarily designed with a width of 0.3 to 8.0 mum and a length of 1.0 to 20.0 mum. A zapping current and a zapping voltage are controlled by changing the width and length of the resistor. | ||||||
| 69 | 전력증폭기 | KR1020120052268 | 2012-05-17 | KR101413200B1 | 2014-06-27 | 오카무라아쓰시; 야마모토카즈야; 마쓰즈카타카유키 |
| 중저출력 동작시에도 동작 효율을 충분히 향상시킬 수 있는 전력증폭기를 얻는다. 증폭 소자 Tr1, Tr2의 베이스에는 입력 신호가 입력되고, 콜렉터에는 콜렉터 전압이 인가되고, 에미터는 접지되어 있다. 바이어스 회로 Bias1, Bias2는, 바이어스 전류를 증폭 소자 Tr1, Tr2의 베이스에 공급한다. 바이어스 회로 Bias1, Bias2는, 콜렉터 전압이 소정의 임계값보다 낮아지면 바이어스 전류를 저감시키는 바이어스 전류 저감회로(12)를 갖는다.
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| 70 | 증폭 장치, 증폭 시스템 및 증폭 방법 | KR1020067010732 | 2004-11-17 | KR1020060094982A | 2006-08-30 | 글라스케빈; 스미스말콤 |
| An amplifier includes a Darlington transistor pair (110, 120) and a biasing network to increase bias currents in an input transistor (110). Circuit (100) includes in put transistor (110), second transistior (120), radio frequency (RF) choke (112), degeneration inductor (122), capacitopr (132) and voltage controlled current source (130). Input transistor (110) and second transistor (120) are coupled to form a Darlington transistor pair with the collectors coupled together at node (142), and the emitter of input transistor (120) at node (111). | ||||||
| 71 | 파워 증폭기 장치 | KR1020000003901 | 2000-01-27 | KR1020000071299A | 2000-11-25 | 세르바에장 |
| 입력전극, 공통전극및 출력전극을가지며도전형이동일한 4개의트랜지스터(11 내지 14; 19 내지 22)를갖는 2개의트랜지스터쌍(1, 2; 3, 4)중적어도한 세트를포함하며, 상기각 트랜지스터쌍(1, 2; 3, 4)은종속접속된입력트랜지스터(11, 13; 19, 21) 및출력트랜지스터(12, 14; 20, 22)를포함하며, 상기입력트랜지스터(11, 13; 19, 21)의출력전극은상기출력트랜지스터(12, 14; 20, 22)의입력전극에결합되며, 상기 2개의트랜지스터쌍(1, 2; 3, 4) 모두의상기입력트랜지스터(11, 13; 19, 21)의상기입력전극에입력신호를인가하는수단(5)이제공되며, 상기 2개의트랜지스터쌍(1, 2; 3, 4) 모두는 2개의상이한전압원(6, 7; 8, 9)에의해바이어스되며, 한전압원(6, 8)의전압으로부터다른전압원(7, 9)의전압으로전환시키는(switching over) 제어수단이제공되며, 제1 트랜지스터쌍(1; 4)의트랜지스터(11 및 12; 19 및 20)는달링턴회로구성으로접속되어있는 G급타입의증폭기에있어서, 상기세트중제2 트랜지스터쌍(2; 3)의트랜지스터(13 및 14; 21 및 22) 모두는서로분리된공통전극을가지며, 상기제2 트랜지스터쌍(2 또는 3)의상기입력트랜지스터(13 또는 21)의상기공통전극은상기제1 트랜지스터쌍(1; 4)의상기입력트랜지스터(11; 19)의상기출력전극에결합되며, 상기제2 트랜지스터쌍(2; 3)의상기출력트랜지스터(14; 22)의상기공통전극은상기제1 트랜지스터쌍(1; 4)의상기출력트랜지스터(12; 20)의상기출력전극에결합되는 G급타입의증폭기가제공된다. | ||||||
| 72 | ESD PROTECTION CIRCUITS | PCT/US2006036552 | 2006-09-19 | WO2007035777A3 | 2009-05-07 | MA YINTAT; LI GUANN-PYNG |
| Improved protection circuits are provided for use as voltage overload protection circuits, ESD protection circuits for RF input pins, and unit protection cells for distributed amplifiers. Preferably, the protection circuits include a positive threshold voltage trigger used to trigger a switch wherein the trigger includes a diode string in series with a resistor and the switch includes a bipolar transistor switch in series with a single reverse diode. Alternatively, the trigger includes a diode string in series with a single diode and a single resistor, and is used to trigger a Darlington pair transistor switch in series with a single reverse diode. In another embodiment, a Darlington pair transistor switch is triggered by a capacitor. In use with distributive amplifiers, the ESD protection circuits are preferably absorbed inside the artificial transmission lines of the distributed amplifier. | ||||||
| 73 | HIGH-VOLTAGE IMPULSE AMPLIFIER | PCT/US2009039483 | 2009-04-03 | WO2009146133A3 | 2010-01-21 | HALDER SUBRATA; JIN RENFENG; HWANG JAMES C M |
| A circuit includes a first transistor in a common-collector configuration and a heterojunction bipolar transistor (HBT) in a common-emitter configuration. The first transistor has a base coupled to an input node for receiving a pulsed signal. A collector of the first transistor is coupled to a first voltage source node. A base of the HBT is coupled to an emitter of the first transistor. A collector of the HBT is coupled to a second voltage source node configured to bias the HBT normally off. The HBT operating isothermally when the pulsed signal has a short-pulse width and a low duty cycle. The first transistor drives the HBT when the pulsed signal is received at the base of the first transistor to output an amplified pulsed signal at the collector of the HBT. | ||||||
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