| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | Esd protection circuit | JP2008531442 | 2006-09-19 | JP2009513040A | 2009-03-26 | インタット マ，; グアン−ピン リー， |
| 電圧過負荷保護回路、ＲＦ入力ピン用ＥＳＤ保護回路、および分布増幅器用ユニット保護セルとして使用するための、改善された保護回路が提供される。 好ましくは、上記保護回路は、スイッチをトリガするために使用される正閾値電圧トリガを含み、該トリガは抵抗器と直列のダイオードストリングを含み、該スイッチは単一のリバースダイオードと直列のバイポーラトランジスタを含む。 あるいは、前記トリガは、単一のダイオードと単一の抵抗器とを含み、単一のリバースダイオードと直列のダーリントンペアトランジスタをトリガするために使用される。 別の実施形態では、ダーリントンペアトランジスタスイッチはコンデンサによりトリガされる。 分布増幅器との使用において、上記ＥＳＤ保護回路は、好ましくは分布増幅器の擬似伝送線内に組み込まれる。 | ||||||
| 42 | AMPLIFIER | US15964776 | 2018-04-27 | US20180316323A1 | 2018-11-01 | Yoshiyuki SUGIMOTO |
| An amplifier that amplifies a differential signal includes first and second input terminals for receiving two input signals; first and second diodes each including anode and cathode, the anodes being electrically connected to the first and second input terminals; first and second bias current sources being respectively electrically connected to the cathodes of the first and second diodes; an operational amplifier connected to the cathode of the first diode and the cathode of the second diode and configured to amplify a differential signal between signals generated at the cathodes of the first and second diodes; a capacitive element being electrically connected between an input and an output of the operational amplifier; and a differential amplifier provided between the operational amplifier and the first and second input terminals and configured to amplify the two input signals. The first and second bias current sources include a current mirror circuit. | ||||||
| 43 | TRANSCONDUCTANCE AMPLIFIER HAVING LOW DISTORTION | US15162963 | 2016-05-24 | US20170346454A1 | 2017-11-30 | David J. Menacher |
| A low distortion transconductance amplifier provides current to a grounded load using a virtual ground input stage, a pair of current mirrors, and a bias current source. The virtual ground input stage may include transistors arranged as a Darlington pair. The low distortion transconductance amplifier can function as a voltage-controlled AC current source that is operable at high frequencies. | ||||||
| 44 | APPARATUS AND METHODS FOR RADIO FREQUENCY AMPLIFIERS | US15265047 | 2016-09-14 | US20170070198A1 | 2017-03-09 | Alan William Ake; David C. Dening |
| Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin. | ||||||
| 45 | Apparatus and methods for radio frequency amplifiers | US14457965 | 2014-08-12 | US09584078B2 | 2017-02-28 | Alan William Ake; David C. Dening |
| Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin. | ||||||
| 46 | Apparatus and methods for electronic amplification | US13462517 | 2012-05-02 | US08836433B2 | 2014-09-16 | David Dening; Alan W Ake |
| Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved. | ||||||
| 47 | Bias point setting for third order linearity optimization of class A amplifier | US12959970 | 2010-12-03 | US08305148B2 | 2012-11-06 | Gregory A. Fung |
| An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation (IM3) products. In an embodiment of a Class A amplifier, the linear amplifier is a bipolar, common emitter-configured (CE) transistor using a cascode transistor to provide a fixed collector bias voltage to the CE transistor. The CE transistor has a transconductance vs. base-emitter voltage (VBE) characteristic which, when plotted, shows a transconductance that increases with an increasing VBE to a maximum, then drops, then tapers off, wherein there is an inflection point between the maximum transconductance and where the transconductance tapers off. A DC bias circuit provides a DC bias voltage to the base of the CE transistor that causes the CE transistor's operating point to track the inflection point over a range of temperatures. This operating point causes the IM3 products to be greatly reduced. | ||||||
| 48 | High-voltage impulse amplifier | US12922491 | 2009-04-03 | US08183933B2 | 2012-05-22 | Subrata Halder; Renfeng Jin; James C.M. Hwang |
| A circuit includes a first transistor in a common-collector configuration and a heterojunction bipolar transistor (HBT) in a common-emitter configuration. The first transistor has a base coupled to an input node for receiving a pulsed signal. A collector of the first transistor is coupled to a first voltage source node. A base of the HBT is coupled to an emitter of the first transistor. A collector of the HBT is coupled to a second voltage source node configured to bias the HBT normally off. The HBT operating isothermally when the pulsed signal has a short-pulse width and a low duty cycle. The first transistor drives the HBT when the pulsed signal is received at the base of the first transistor to output an amplified pulsed signal at the collector of the HBT. | ||||||
| 49 | TRIPLET TRANSCONDUCTOR | US13074051 | 2011-03-29 | US20110316635A1 | 2011-12-29 | Kevin W. Kobayashi |
| To reduce a knee voltage of a Darlington amplifier, a negative voltage is applied by a depletion mode FET between the emitter of one amplifying transistor and the base of another amplifying transistor to provide a reduced potential, which reduces the knee voltage of the Darlington amplifier. Reducing the knee voltage of the Darlington amplifier decreases the size of a saturation region thereby increasing the linearity of the Darlington amplifier. | ||||||
| 50 | Active bias Darlington amplifier | US12245949 | 2008-10-06 | US07772927B1 | 2010-08-10 | Jeffrey B. Shealy; Philip M. Garber |
| The present invention relates to an active bias Darlington pair amplifier that may operate without a traditional bias resistor. The active bias Darlington pair amplifier includes an output transistor element that is cascaded with and driven from a driver transistor element. Active bias circuitry provides bias to the driver transistor element to regulate bias current in the output transistor element. The bias current in the output transistor element is sensed by the active bias circuitry. The active bias circuitry may include alternating current (AC) circuitry, which may adjust bias under certain radio frequency (RF) drive conditions. The active bias Darlington pair amplifier may include feedback circuitry, which provides feedback from the output transistor element to the driver transistor element. The feedback circuitry may include AC circuitry, which may provide frequency dependent feedback. | ||||||
| 51 | GAIN-CONTROLLED LOW NOISE AMPLIFIER MEANS | US12302212 | 2007-05-15 | US20090174483A1 | 2009-07-09 | Leonardus Henricus Maria Hesen; Edwin Adrianus Johannes Beekmans |
| A gain-controlled low noise amplifier means is provided. The amplifier means comprises an amplifier (T1), a first and second pin diode (D1, D2) coupled in series with opposite forward directions in a negative feedback loop of the amplifier (T1) between an input and an output of the amplifier (T1). The amplifier means furthermore comprises a first current source (IC1) coupled to a node between the first and second pin diode (D1, D2) and a second current source (IC2) coupled to an input of the amplifier (T1). | ||||||
| 52 | Enhancement-depletion Darlington device | US11422928 | 2006-06-08 | US07439805B1 | 2008-10-21 | Kevin W. Kobayashi |
| An apparatus comprising a Darlington transistor pair comprising a first transistor and a second transistor. The first transistor may have a gate configured to receive an input signal. The second transistor may have a gate coupled to a source of the first transistor. The Darlington transistor pair may be configured to generate an output signal at a drain of the first transistor and a drain of the second transistor in response to the input signal. The first transistor may be implemented as an enhancement mode device and the second transistor may be implemented as a depletion mode device. | ||||||
| 53 | Control circuit for controlling a current and/or voltage of an electronic circuit | US11785552 | 2007-04-18 | US20070229160A1 | 2007-10-04 | Franz Beck |
| A control circuit is provided for controlling a current and/or voltage of an electronic circuit. The circuit comprises an input stage, which has at least one input, a supply voltage terminal, an amplifier element, and a subcircuit. The amplifier element comprises an operating current path and a control terminal. In the circuit, the subcircuit applies a bias to the control terminal and the input is connected to the latter. The control circuit is characterized in that the subcircuit provides a bias, which is independent of a supply voltage applied to the supply voltage terminal and of a current amplification of the amplifier element. | ||||||
| 54 | Power amplifier arrangement | US09466789 | 1999-12-20 | US06204730B1 | 2001-03-20 | Jan Servaes |
| Amplifier of the G class type, comprising at least one set of two transistor pairs (1,2; 3,4) having together four transistors (11 to 14; 19 to 22) of the same conductivity type with an input electrode, a common electrode and an output electrode, each pair (1,2; 4,3) comprising an input transistor (11,13; 19,21) and an output transistor (12,14; 20,22) in cascade, the output electrode of the input transistor (11,13; 19,21) being coupled to the input electrode of the output transistor (12,14; 20,22), whereby further means (5) are provided for applying an input signal to the input electrodes of the input transistors (11,13; 19,21) of both pairs and both pairs (1,2; 3,4) are biased by two different voltage supplies (6,7; 8,9), control means being provided for switching over from the voltage of one voltage supply (6; 8) to the voltage of the other voltage supply (7; 9), the transistors (11 and 12; 19 and 20) of the first pair (1; 4) of a set being connected in a Darlington circuit arrangement while both transistors (13 and 14; 21 and 22) of the second pair (2; 3) have their common electrodes separated from each other, the common electrode of the input transistor (13 or 21) of the second pair (2 or 3) being coupled to the output electrode of the input transistor (11; 19) of the first pair (1; 4) and the common electrode of the output transistor (14; 22) of the second pair (2; 3) being coupled to the output electrode of the output transistor (12; 20) of the first pair (1; 4). | ||||||
| 55 | OUTPUT CIRCUIT OF AMPLIFIER | EP16891400.0 | 2016-02-22 | EP3404830A1 | 2018-11-21 | Akaishi, Takeshi |
Provided is an output circuit of an amplifier, said output circuit not changing power consumption. Since the output circuit of the amplifier does not flow, to a power supply circuit, a current correlated to a signal, the output circuit is not affected by the power supply circuit. The output circuit of the amplifier is provided with: a three-terminal amplifying element having an input terminal, an output terminal, and a common terminal; and a constant current circuit, which is connected to the common terminal, and which flows a substantially constant current to the three-terminal amplifying element. The output terminal is grounded, and amplified output is taken out between the output terminal, and a contact point between the common terminal and the constant current circuit. Since the consumption current of the output circuit of the amplifier is merely a current flowing in the constant current circuit, there is no consumption current change correlated to the output current. |
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| 56 | BIAS POINT SETTING FOR THIRD ORDER LINEARITY OPTIMIZATION OF CLASS A AMPLIFIER | EP11793633.6 | 2011-11-29 | EP2647123B1 | 2016-11-02 | FUNG, Gregory A. |
| 57 | BIAS POINT SETTING FOR THIRD ORDER LINEARITY OPTIMIZATION OF CLASS A AMPLIFIER | EP11793633.6 | 2011-11-29 | EP2647123A1 | 2013-10-09 | FUNG, Gregory A. |
| An actual linear amplifier distorts an input signal, such as an RF signal, and generates third order intermodulation, IM3, products. In an embodiment of a Class A amplifier, the linear amplifier is a bipolar, common emitter- configured, CE, transistor (40) using a cascode transistor (16) to provide a fixed collector bias voltage to the CE transistor (40). The CE transistor (40) has a transconductance vs. base -emitter voltage, VBE, characteristic which, when plotted, shows a transconductance that increases with an increasing VBE to a maximum, then drops, then tapers off, wherein there is an inflection point between the maximum transconductance and where the transconductance tapers off. A DC bias circuit (34) provides a DC bias voltage to the base of the CE transistor (40) that causes the CE transistor?s operating point to track the inflection point over a range of temperatures. This operating point causes the IM3 products to be greatly reduced. | ||||||
| 58 | ESD PROTECTION CIRCUITS | EP06814981 | 2006-09-19 | EP1927174A4 | 2010-05-26 | MA YINTAT; LI GUANN-PYNG |
| 59 | Ansteuerschaltung einer Strom und/oder Spannungssteuerung einer elektronischen Schaltung | EP05800646.1 | 2005-10-13 | EP1805889A1 | 2007-07-11 | BECK, Franz |
| The invention relates to a control circuit (10) for controlling the current and/or voltage of an electronic circuit (12). Said circuit comprises an input stage (72), which has at least one input (68), a supply voltage terminal (76), an amplifier element (78) and a partial circuit (80), said amplifier element (78) comprising a working current section and a control current terminal (82). In said circuit, the partial circuit (80) applies a bias to the control current terminal (82) and the input (68) is connected to the latter (82). The control circuit is characterised in that the partial circuit (80) provides a bias, which is independent of a bias that is applied to the supply voltage terminal (76) and of a current amplification created by the amplifier element (78). | ||||||
| 60 | 増幅回路 | JP2017090051 | 2017-04-28 | JP2018191068A | 2018-11-29 | 杉本 良之 |
| 【課題】低消費電力化が可能な増幅回路を実現する。 【解決手段】帰還用アンプ30は、一方の入力信号が入力される入力端子INPと、他方の入力信号が入力される入力端子INNと、入力端子INP,INN側にアノードが接続されたダイオード対53と、ダイオード対53のカソードにそれぞれ接続され、ダイオード対53のそれぞれに電流を供給するバイアス電流源54と、ダイオード対53のカソードに接続され、ダイオード対53のカソードに生じた信号の差信号を増幅するCMOS構成のオペアンプ56と、オペアンプ56の入出力間に接続された容量素子57と、オペアンプ56と入力端子INP,INNとの間に設けられ、入力信号を増幅するバイポーラトランジスタ対63a,63bを含む差動アンプ52とを備え、バイアス電流源54は、カレントミラー回路部55を含む。 【選択図】図2 |
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