| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 功率放大器 | CN201210172596.4 | 2012-05-30 | CN102811023B | 2015-06-03 | 冈村笃司; 山本和也; 松塚隆之 |
| 本发明提供一种即使在中低输出工作时也能使工作效率充分提高的功率放大器。给放大元件(Tr1、Tr2)的基极输入输入信号，并且给集电极施加集电极电压，发射极接地。偏置电路(Bias1、Bias2)给放大元件(Tr1、Tr2)的基极供给偏置电流。偏置电路(Bias1、Bias2)具有当集电极电压变得比规定的阈值低时使偏置电流降低的偏置电流降低电路(12)。 | ||||||
| 2 | 增益控制低噪声放大器装置 | CN200780018897.9 | 2007-05-15 | CN101454972A | 2009-06-10 | 莱昂纳德斯·H·M·海森; 埃德温·A·J·比克曼斯 |
| 提供了一种增益控制低噪声放大器装置。放大器装置包括：放大器单元(T1)；第一和第二pin二极管(D1，D2)，在放大器(T1)的输入与输出之间以相反的正向将所述第一和第二pin二极管(D1，D2)串联在放大器单元(T1)的负反馈回路中。放大器装置还包括：第一电流源(IC1)，所述第一电流源(IC1)与第一和第二pin二极管(D1，D2)之间的节点连接；以及第二电流源(IC2)，所述第二电流源(IC2)与放大器单元(T1)的输入连接。 | ||||||
| 3 | ESD保护电路 | CN200680043082.1 | 2006-09-19 | CN101517671B | 2013-04-10 | Y·马; G·-P·李 |
| 提供了改进的保护电路用作电压过载保护电路、RF输入管脚的ESD保护电路以及分布式放大器的单位保护单元。优选地，该保护电路包括用以触发开关的正阈值电压触发器，其中该触发器包括与电阻器串联的二极管串，并且所述开关包括与单反向二极管串联的双极型晶体管开关。可选地，该触发器包括与单二极管和单电阻器串联的二极管串，并且用来触发与单反向二极管串联的复合晶体管对晶体管开关。在另一实施例中，复合晶体管对晶体管开关由电容器触发。在与分布式放大器使用时，该ESD保护电路优选被吸入到分布式放大器的仿真传输线内。 | ||||||
| 4 | 功率放大器 | CN201210172596.4 | 2012-05-30 | CN102811023A | 2012-12-05 | 冈村笃司; 山本和也; 松塚隆之 |
| 本发明提供一种即使在中低输出工作时也能使工作效率充分提高的功率放大器。给放大元件(Tr1、Tr2)的基极输入输入信号，并且给集电极施加集电极电压，发射极接地。偏置电路(Bias1、Bias2)给放大元件(Tr1、Tr2)的基极供给偏置电流。偏置电路(Bias1、Bias2)具有当集电极电压变得比规定的阈值低时使偏置电流降低的偏置电流降低电路(12)。 | ||||||
| 5 | ESD保护电路 | CN200680043082.1 | 2006-09-19 | CN101517671A | 2009-08-26 | Y·马; G·-P·李 |
| 提供了改进的保护电路用作电压过载保护电路、RF输入管脚的ESD保护电路以及分布式放大器的单位保护单元。优选地，该保护电路包括用以触发开关的正阈值电压触发器，其中该触发器包括与电阻器串联的二极管串，并且所述开关包括与单反向二极管串联的双极型晶体管开关。可选地，该触发器包括与单二极管和单电阻器串联的二极管串，并且用来触发与单反向二极管串联的复合晶体管对晶体管开关。在另一实施例中，复合晶体管对晶体管开关由电容器触发。在与分布式放大器使用时，该ESD保护电路优选被吸入到分布式放大器的仿真传输线内。 | ||||||
| 6 | 用于电子射线的电聚焦的电源 | CN201410654059.2 | 2014-09-24 | CN104597954B | 2017-08-04 | J·德林格; J·奥尔施莱格尔 |
| 本发明涉及具有高压末级的、用于电聚焦电子射线的可快速调节的高压电源。该高压末级具有多个放大器元件，它们与第一高压连接端子串联连接；具有一系列分压器元件的分压器链，所述分压器元件与第一高压连接端子连接并且与放大器元件处于信号连接中，使得在该分压器链上施加电压的情况下在放大器元件的信号输入端和分别下一放大器元件的信号输入端之间的电压的差分别具有相同的符号。 | ||||||
| 7 | 用于电子射线的电聚焦的电源 | CN201410654059.2 | 2014-09-24 | CN104597954A | 2015-05-06 | J·德林格; J·奥尔施莱格尔 |
| 本发明涉及具有高压末级的、用于电聚焦电子射线的可快速调节的高压电源。该高压末级具有多个放大器元件，它们与第一高压连接端子串联连接；具有一系列分压器元件的分压器链，所述分压器元件与第一高压连接端子连接并且与放大器元件处于信号连接中，使得在该分压器链上施加电压的情况下在放大器元件的信号输入端和分别下一放大器元件的信号输入端之间的电压的差分别具有相同的符号。 | ||||||
| 8 | 用于高功率的恒定电流达林顿电路 | CN200580037562.2 | 2005-11-04 | CN101053150A | 2007-10-10 | 秦玉相 |
| 本发明公开了一种高功率恒定电流达林顿电路，包括输入端子，其中，恒定电流达林顿电路的基极端子(B)(第一端子)连接到晶体管(Q1)的基极，晶体管(Q1)的发射极连接到电阻器(R1)的一端和晶体管(Q2)的基极，电阻器(R1)的另一端连接到晶体管(Q3)的发射极，恒定电流达林顿电路的集电极端子(C)(第二端子)连接到晶体管(Q1)的集电极和晶体管(Q2)的集电极，晶体管(Q2)的发射极连接到恒定电压源(CV1)的一端，恒定电流达林顿电路的发射极端子(E)(第三端子)直接连接到负载(LD1)，恒定电压源(CV1)的另一端连接到电阻器(R2)的一端和晶体管(Q3)的基极，并且恒定电流达林顿电路的端子(E1)(第四端子)连接到电阻器(R2)的另一端和晶体管(Q3)的集电极，从而最小化输出端子的功率损耗，本发明还公开了一种集成了该结构的半导体设备。 | ||||||
| 9 | 电子电路的电流和/或电压控制的控制电路 | CN200580035663.6 | 2005-10-13 | CN101044675A | 2007-09-26 | 弗伦茨·贝克 |
| 提出了一种电子电路(12)的电流和/或电压控制的控制电路(10)，具有输入级(72)，该输入级具有至少一个输入端(68)，一个供电电压端子(76)，一个放大器元件(78)和一个部分电路(80)，其中放大器元件(78)具有工作电流区段和控制端子(82)，其中所述部分电路(80)将偏压施加到控制端子(82)上，并且其中所述输入端(68)与所述控制端子(82)相连接。控制电路的特征在于，部分电路(80)提供偏压，该偏压与施加于供电电压端子(76)上的供电电压以及放大器元件(78)的电流增益无关。 | ||||||
| 10 | 熔断电路 | CN200610143570.1 | 2006-11-09 | CN101005069A | 2007-07-25 | 大竹诚治 |
| 在本发明的一种熔断电路中，作为熔断元件使用了由多晶硅膜或钨硅膜构成的电阻(5～9)，作为将电阻(5～9)的一部分或全部熔断的驱动元件，使用低耐压的MOS晶体管(10～14)。因而，通过使用MOS晶体管(10～14)，可以缩小驱动元件的形成区域，可以减小IC芯片的面积。本发明能够解决在现有的电流调整电路中，因将齐纳二极管作为熔断元件而使用高耐压的双极性晶体管，所以存在不能高效率地利用IC芯片面积的问题。 | ||||||
| 11 | Linear FET feedback amplifier | US14790096 | 2015-07-02 | US09722552B2 | 2017-08-01 | Kevin Wesley Kobayashi |
| A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network. | ||||||
| 12 | LINEAR FET FEEDBACK AMPLIFIER | US14790096 | 2015-07-02 | US20160013766A1 | 2016-01-14 | Kevin Wesley Kobayashi |
| A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network. | ||||||
| 13 | APPARATUS AND METHODS FOR RADIO FREQUENCY AMPLIFIERS | US14457965 | 2014-08-12 | US20140347136A1 | 2014-11-27 | Alan William Ake; David C. Dening |
| Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin. | ||||||
| 14 | Internally, Resistively, Sensed Darlington Amplifier | US13827139 | 2013-03-14 | US20140266466A1 | 2014-09-18 | Joseph Cuggino |
| An internally, resistively, sensed Darlington amplifier includes a Darlington amplifier, at least an input transistor, an output transistor, a resistive divider, a signal input node, and a signal output node. The Darlington amplifier is responsive to an input signal and configured to generate an output signal. An internal bias setting resistor is coupled between the signal output node, a collector of the output transistor, and the resistive divider. The bias setting resistor is configured to set and regulate the bias current of the Darlington amplifier. | ||||||
| 15 | POWER AMPLIFIER | US13301955 | 2011-11-22 | US20120306579A1 | 2012-12-06 | Atsushi OKAMURA; Kazuya Yamamoto; Takayuki Matsuzuka |
| A power amplifier includes: an amplifying element having a base into which input signals are inputted, a collector to which a collector voltage is applied, and an emitter; and a bias circuit supplying a bias current to the base of the amplifying element. The bias circuit includes a bias current lowering circuit which lowers the bias current when the collector voltage is lower than a prescribed threshold value. | ||||||
| 16 | Triplet transconductor | US13074051 | 2011-03-29 | US08248166B2 | 2012-08-21 | Kevin W. Kobayashi |
| To reduce a knee voltage of a Darlington amplifier, a negative voltage is applied by a depletion mode FET between the emitter of one amplifying transistor and the base of another amplifying transistor to provide a reduced potential, which reduces the knee voltage of the Darlington amplifier. Reducing the knee voltage of the Darlington amplifier decreases the size of a saturation region thereby increasing the linearity of the Darlington amplifier. | ||||||
| 17 | HIGH-VOLTAGE IMPULSE AMPLIFIER | US12922491 | 2009-04-03 | US20110006847A1 | 2011-01-13 | Subrata Halder; Renfeng Jin; James C.M. Hwang |
| A circuit includes a first transistor in a common-collector configuration and a heterojunction bipolar transistor (HBT) in a common-emitter configuration. The first transistor has a base coupled to an input node for receiving a pulsed signal. A collector of the first transistor is coupled to a first voltage source node. A base of the HBT is coupled to an emitter of the first transistor. A collector of the HBT is coupled to a second voltage source node configured to bias the HBT normally off. The HBT operating isothermally when the pulsed signal has a short-pulse width and a low duty cycle. The first transistor drives the HBT when the pulsed signal is received at the base of the first transistor to output an amplified pulsed signal at the collector of the HBT. | ||||||
| 18 | Constant Current Darlington Circuits for High Power | US11666005 | 2005-11-04 | US20080129380A1 | 2008-06-05 | Ok-Sang Jin |
| Disclosed herein is a high-power constant current Darlington circuit, including an input terminal in which the base terminal (B) (a first terminal) of the constant current Darlington circuit is connected to the base of a transistor (Q1), the emitter of the transistor (Q1) being connected to one end of a resistor (R1) and the base of a transistor (Q2), the other end of the resistor (R1) being connected to an emitter of the transistor (Q3), the collector terminal (C) (a second terminal) of the constant current Darlington circuit connected to the collector of the transistor (Q1) and the collector of the transistor (Q2), the emitter of the transistor (Q2) being connected to one end of a constant voltage source (CV1), the emitter terminal (E) (a third terminal) of the constant current Darlington circuit directly connected to a load (LD1), the other end of the constant voltage source (CV1) being connected to one end of a resistor (R2) and the base of the transistor (Q3), and the terminal (E1) (a fourth terminal) of the constant current Darlington circuit connected to the other end of the resistor (R2) and the collector of the transistor (Q3), thereby minimizing the loss of power of an output terminal, and a semiconductor device into which the construction is integrated. | ||||||
| 19 | 低い歪みを有するトランスコンダクタンス増幅器 | JP2017101486 | 2017-05-23 | JP2017212735A | 2017-11-30 | デビッド ジェイ メナヒャー |
| 【課題】高周波数で動作可能である電圧制御AC電流源として機能することができる低歪みトランスコンダクタンス増幅器を提供する。 【解決手段】低歪みトランスコンダクタンス増幅器121は、仮想接地入力段110c、一対の電流ミラー108a、108b及びバイアス電流源Ibを使用して、出力電流Ioutを接地負荷104に提供する。仮想接地入力段110cは、ダーリントンペアとして配設されるトランジスタ122を含む。 【選択図】図6 |
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| 20 | 電力増幅器 | JP2011121491 | 2011-05-31 | JP5673361B2 | 2015-02-18 | 篤司 岡村; 山本 和也; 和也 山本; 松塚 隆之; 隆之 松塚 |
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