| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 161 | Apparatus and method for improving power supply rejection ratio | US14702586 | 2015-05-01 | US09401679B1 | 2016-07-26 | Sharad Vijaykumar |
| A compensation capacitor can be added to an amplifier for stability. Disclosed are systems and methods for improving the power supply rejection ratio (PSRR) performance of an amplifier in the presence of one or more compensation capacitors. | ||||||
| 162 | AMPLIFIER AND RELATED METHOD | US14922208 | 2015-10-26 | US20160142027A1 | 2016-05-19 | Chi-Yao Yu; Chung-Yun Chou |
| An amplifier applicable to an intra-band non-contiguous carrier aggregation (NCCA) band includes a first amplifier circuit and a second amplifier circuit. The NCCA band includes at least a primary component carrier (PCC) channel and a secondary component carrier (SCC) channel not adjacent to each other. The first amplifier circuit receives a first input signal, and generates a first output signal for undergoing down-conversion of one of the PCC channel and the SCC channel. The second amplifier circuit receives at least one second input signal, and generates a second output signal for undergoing down-conversion of another of the PCC channel and the SCC channel. The at least one second input signal received by the second amplifier circuit is provided by the first amplifier circuit according to the first input signal. | ||||||
| 163 | OPERATIONAL AMPLIFIER BASED CIRCUIT WITH COMPENSATION CIRCUIT BLOCK USED FOR STABILITY COMPENSATION | US14920894 | 2015-10-23 | US20160142016A1 | 2016-05-19 | Chi-Yao Yu |
| An operational amplifier based circuit has an operational amplifier, a feedback circuit, and a compensation circuit block. The feedback circuit is coupled between an output port and an input port of the operational amplifier. The compensation circuit block has circuits involved in stability compensation of the operational amplifier, wherein there is no stability compensation circuit driven at the output port of the operational amplifier. | ||||||
| 164 | SILICON PHOTONICS MODULATOR DRIVER | US14698974 | 2015-04-29 | US20160112016A1 | 2016-04-21 | Kadaba LAKSHMIKUMAR; Craig APPEL |
| Embodiments generally relate to a conversion arrangement, a driver arrangement, and a method of producing a complementary complementary metal-oxide-semiconductor (CMOS) output signal for driving a modulator device. The conversion arrangement includes a differential amplifier configured to produce a first amplified signal based on the differential input signal, and at least two transimpedance amplifiers (TIAs) coupled with respective outputs of the differential amplifier and configured to produce a second amplified signal based on the first amplified signal. Respective bias voltages for the TIAs are based on the first amplified signal. The conversion arrangement further includes a common-mode feedback arrangement coupled with outputs of the TIAs and configured to control the first amplified signal based on the second amplified signal, thereby controlling the bias voltages, wherein the complementary CMOS output signal is based on the second amplified signal. | ||||||
| 165 | Low-noise amplifier | US14375127 | 2013-01-25 | US09312818B2 | 2016-04-12 | Sven Mattisson; Stefan Andersson |
| A common source or common emitter LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises an input transistor arranged to, in operation, be biased to have a transconductance gm at the operating frequency f, and having a first terminal, which is a gate or base terminal, operatively connected to an input terminal of the LNA circuit. The LNA circuit further comprises a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor. Furthermore, the LNA circuit comprises an output capacitor operatively connected between the second terminal of the input transistor and an output terminal of the LNA circuit. The output capacitor has a capacitance value CL | ||||||
| 166 | Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source-gate LNA | US14108312 | 2013-12-16 | US09287836B2 | 2016-03-15 | Zaw Soe |
| A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra. | ||||||
| 167 | Amplifier | US14321859 | 2014-07-02 | US09214903B2 | 2015-12-15 | Shinichi Miwa; Kunihiro Sato |
| An amplifier includes a transistor chip, a matching chip with a capacitor group having multiple MIM capacitors, each of the MIM capacitors including a lower electrode, a dielectric, and an upper electrode, a bonding wire that electrically connects the transistor chip to the upper electrode of any one of the MIM capacitors of the capacitor group and transmits a high-frequency signal, and a case that accommodates the transistor chip and the matching chip. The lower electrodes of the MIM capacitors are grounded, and capacitance values of each of the MIM capacitors of the capacitor group are different from each other. | ||||||
| 168 | CASCODE AMPLIFIER | US14436633 | 2012-11-09 | US20150340997A1 | 2015-11-26 | Katsuya KATO; Miyo MIYASHITA; Toshihide OKA; Kenichi HORIGUCHI; Kazutomi MORI; Kenji MUKAI; Takanobu FUJIWARA |
| A plurality of source-grounded transistors (3) are connected in parallel with each other, and a plurality of gate-grounded transistors (4) are connected in parallel with each other. Sources (4s) of the plurality of gate-grounded transistors (4) are connected to drains (3d) of the plurality of source-grounded transistors (3) respectively. Ground pads (5) are connected to sources (3s) of the plurality of source-grounded transistors (3). A plurality of grounding capacitances (6) are connected between gates (4g) of the plurality of gate-grounded transistors (4) and the ground pads (5). The plurality of source-grounded transistors (3) and the plurality of grounding capacitances (6) are alternately arranged between the ground pads (5) and the plurality of gate-grounded transistors (4). | ||||||
| 169 | Cascode power amplifier | US14028844 | 2013-09-17 | US09118284B1 | 2015-08-25 | James J. Komiak |
| An amplifier for amplifying signals is presented. A cascode power amplifier includes two or more adjacent cascode amplifiers and at least one remote cascode amplifier. The adjacent cascode amplifiers are lined up adjacent each other with inputs of the adjacent cascode amplifiers connected to a common input line and outputs of the of adjacent cascode amplifiers connected to a common output line. The adjacent cascode amplifiers generally operate in parallel. The remote cascode amplifier is spaced apart from the adjacent cascode amplifiers. An input transmission line connects an input of the remote cascode amplifier to the common input line. An output transmission line connects an output of the remote cascode amplifier to the common output line. Amplified outputs of the adjacent cascode amplifiers and amplified outputs of the remote cascode amplifier are power combined and summed into a coherent amplified output signal that is output on the output transmission line. | ||||||
| 170 | Spur cancellation in GSM-GPRS-EDGE power amplifiers with DC-DC converters | US14067548 | 2013-10-30 | US09065385B2 | 2015-06-23 | Oleksandr Gorbachov |
| A radio frequency (RF) power amplifier circuit with spur cancellation for GSM/GPRS/EDGE transceivers is disclosed. There is a power amplifier with an RF input, an RF output, and a voltage supply input. Additionally, there is an adjustable DC-DC converter with an input connected to a battery, an output connected to the voltage supply input of the power amplifier with a DC supply voltage signal generated thereby. A spur compensator generates an error control signal responsive to spurs in the DC supply voltage signal. The error control signal is applied to the RF input of the power amplifier. | ||||||
| 171 | METHOD AND APPARATUS FOR TRANSITIONING A DEVICE BETWEEN OPERATING STATES TO CONTROL POWER CONSUMED BY THE DEVICE | US14492384 | 2014-09-22 | US20150012770A1 | 2015-01-08 | Sasan Cyrusian |
| A method including: accounting for a transition time for a device to transition between two of first, second, and powered off states; generating a control signal based on the transition time; receiving, at the device and from a processor, an output signal and the control signal; and consuming power, via the device, while operating in the first state and the second state. The method further includes: in response to the control signal, transitioning the device to the second state based on a frequency of the output signal or the control signal; subsequent to transitioning to the second state, performing a function based on the first output signal; and subsequent to performing the function, generating an output via the device; generating a feedback signal based on the output; and based on the feedback signal, transitioning the device to either the first state or the powered off state. | ||||||
| 172 | LOW-NOISE AMPLIFIER | US14375127 | 2013-01-25 | US20150002225A1 | 2015-01-01 | Sven Mattisson; Stefan Andersson |
| A common source or common emitter LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises an input transistor arranged to, in operation, be biased to have a transconductance gm at the operating frequency f, and having a first terminal, which is a gate or base terminal, operatively connected to an input terminal of the LNA circuit. The LNA circuit further comprises a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor. Furthermore, the LNA circuit comprises an output capacitor operatively connected between the second terminal of the input transistor and an output terminal of the LNA circuit. The output capacitor has a capacitance value CL | ||||||
| 173 | Circuit for processing a time-discrete analog signal and image sensor | US13116329 | 2011-05-26 | US08830365B2 | 2014-09-09 | Thomas Bellingrath; Michael Hackner |
| A circuit for processing an analog signal having a time sequence of discrete signal levels, each of which lies in a time interval and represents an information-bearing segment of the interval while the rest of the time interval is a non-information-bearing segment, comprises a transistor in emitter-follower or source-follower configuration, a high emitter or source resistance or, instead, a high-ohm constant current source, and a device for applying a voltage supply, as well as a switch which is connected between the emitter and a reference potential to prevent a current from flowing via the high-ohm resistance or the high-ohm voltage source for charge reversal of an output capacitance of the circuit in one direction, whereas for charge reversal in the other direction the dynamic current boosting effect of the transistor is exploited. This results in a fast emitter-follower or source-follower circuit which is particularly suitable as the output stage for image sensors. | ||||||
| 174 | SPUR CANCELLATION IN GSM-GPRS-EDGE POWER AMPLIFIERS WITH DC-DC CONVERTERS | US14067548 | 2013-10-30 | US20140118075A1 | 2014-05-01 | OLEKSANDR GORBACHOV |
| A radio frequency (RF) power amplifier circuit with spur cancellation for GSM/GPRS/EDGE transceivers is disclosed. There is a power amplifier with an RF input, an RF output, and a voltage supply input. Additionally, there is an adjustable DC-DC converter with an input connected to a battery, an output connected to the voltage supply input of the power amplifier with a DC supply voltage signal generated thereby. A spur compensator generates an error control signal responsive to spurs in the DC supply voltage signal. The error control signal is applied to the RF input of the power amplifier. | ||||||
| 175 | APPARATUS FOR POWERING A DEVICE | US14070889 | 2013-11-04 | US20140059364A1 | 2014-02-27 | Sasan Cyrusian |
| An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state. | ||||||
| 176 | Extremely High Frequency Dual-Mode Class AB Power Amplifier | US13591061 | 2012-08-21 | US20130265108A1 | 2013-10-10 | Joos Dieter; Wim Philibert; Patrick Reynaert; Dixian Zhao |
| An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design. | ||||||
| 177 | Amplifier module with multiple operating modes | US13226400 | 2011-09-06 | US08461921B2 | 2013-06-11 | Nathan M Pletcher; Aristotele Hadjichristos; Babak Nejati |
| An amplifier module with multiple operating modes is described. In an exemplary design, an apparatus includes a plurality of amplifiers. The apparatus may also include a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode. Further, the apparatus may include an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches. | ||||||
| 178 | Controlling amplifier input impedance | US12595470 | 2008-04-10 | US08314659B2 | 2012-11-20 | Anthony Lawrence McFarthing |
| An amplifier (22) containing an arrangement of capacitive elements (26, 28) in place of a source degeneration inductor arrangement to set the real part of the amplifier's input impedance. | ||||||
| 179 | DISTRIBUTED AMPLIFIER FOR BAND PASS RADIO FRONT-END | US13388852 | 2010-08-05 | US20120194267A1 | 2012-08-02 | Safieddin Safavi-Naeini; Mahmoud Mohammad-Taheri; Ying Wang; Mehrdad Fahimnia |
| A distributed amplifier is provided that is broadband and band pass with controllable bandwidth. In the distributed amplifier circuit, termination impedance of the input transmission line is not matched with the characteristics impedance of the input transmission line and/or the termination impedance of the output transmission line is not matched with the characteristics impedance of the output transmission line, thus providing the broadband and band pass with controllable bandwidth attributes. | ||||||
| 180 | AMPLIFIER MODULE WITH MULTIPLE OPERATING MODES | US13226400 | 2011-09-06 | US20110316637A1 | 2011-12-29 | Nathan M. Pletcher; Aristotele Hadjichristos; Babak Nejati |
| An amplifier module with multiple operating modes is described. In an exemplary design, an apparatus includes a plurality of amplifiers. The apparatus may also include a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode. Further, the apparatus may include an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches. | ||||||
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