| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | High efficiency linear power amplifiers with load compensation | US12303697 | 2006-06-09 | US07956683B2 | 2011-06-07 | Thomas Lejon |
| The present invention addresses the problem to extend the dynamic power range where the amplifier operates linearly for a full input amplitude swing with improved efficiency. According to the present invention, the above presented problem is solved by changing the delivered power to the load by changing the value of the load and still keeping the amplifier in its linear condition. The invention enables the amplifier to maintain high efficiency over a wider power range. | ||||||
| 182 | Multiband wireless device and semiconductor integrated circuit | US11769151 | 2007-06-27 | US07945232B2 | 2011-05-17 | Yoshikazu Sugiyama; Satoshi Adachi; Yusaku Katsube; Masazumi Tone; Taku Takaki |
| When switching over from a portable telephone system of 800 MHz band to a UWB communication system of 9 GHz band, depending upon a signal for changing over a high pass filter and a low pass filter, a reactance element, which is determined to be matching with a load Z of the high pass filter, is connected to an output terminal of a transmitting power amplifier. With this, it is possible to achieve a multi-band or multi-mode wireless receiver of using a frequency band from 800 MHz to 10 GHz, without an enlargement of a circuit scale and an increase of costs. | ||||||
| 183 | Dual bias control circuit | US11576812 | 2005-10-05 | US07944306B2 | 2011-05-17 | Dmitri Pavlovitch Prikhodko; Remco Ooijman; Pieter Lok; Jeroen Sluijter |
| The present invention relates to a bias control circuit and method for supplying a bias signal to at least one stage of an amplifier circuit, wherein a dual bias control is provided by generating a bias current and additionally using this bias current to derive a control signal for limiting a supply voltage of the at least one amplifier stage in response to the control signal. Thereby, a compression of the output signal of the amplifier stage, which results from the voltage limitation, can be realized in addition to the base current steering. This leads to a decrease in small signal gain and thus reduced output noise. | ||||||
| 184 | BIAS CIRCUIT | US12898164 | 2010-10-05 | US20110080230A1 | 2011-04-07 | Atsushi FUKUDA; Hiroshi Okazaki; Shoichi Narahashi |
| A bias circuit includes: a bias supply terminal 800; a parallel capacitor 3 connected at one end thereof to the bias supply terminal 800 and grounded at the other end thereof; and a parallel circuit 3L connected in parallel with the parallel capacitor 3 and connected at one end thereof to the bias supply terminal 800. Let 2≦N. The parallel circuit 3L includes: a direct-current power supply connection terminal 600; N parallel inductors 21 to 2N connected in series with each other between the bias supply terminal 800 and the direct-current power supply connection terminal 600; and N−1 series resonators 91 to 9N−1. Each series resonator 91 to 9N−1 includes: a resonant capacitor 71 to 7N−1 connected at one end thereof to a connecting point between adjacent parallel inductors; and a resonant inductor 81 to 8N−1 connected at one end thereof to the other end of the resonant capacitor 71 to 7N−1 and grounded at the other end thereof. | ||||||
| 185 | Field effect transistor amplifier with linearization | US10920526 | 2004-08-17 | US07853235B2 | 2010-12-14 | Vladimir Aparin |
| An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance. | ||||||
| 186 | Method and apparatus for improving the performance of MIMO wireless systems | US12067915 | 2006-09-26 | US07782132B2 | 2010-08-24 | Eli Plotnik; Avner Elia |
| Method and apparatus for efficiently providing DC power enhancement to power amplifiers each of which being arranged in a MIMO system, by suing an enhancement circuitry with a plurality of inputs and outputs. Each input has a corresponding DC enhancement output that is connected to a DC enhancement input of a power amplifier. The DC enhancement output becomes operative whenever the amplitude of the corresponding input signal exceeds a predetermined threshold. The envelope of a plurality of input signals is sampled by sampling circuitries and the sampled envelopes are fed into a summation circuitry, in which they are summed. Whenever one of the sampled envelopes exceeds the threshold, a DC enhancement power is simultaneously provided to all DC enhancement inputs of all power amplifiers. | ||||||
| 187 | Variable gain amplifier and control method thereof | US12058354 | 2008-03-28 | US07567126B2 | 2009-07-28 | Tomoyuki Arai |
| A variable gain amplifier has a first amplifier circuit (106) having a first field-effect transistor and amplifying a signal input to a gate of the first field-effect transistor to output; a gate bias control circuit (102) controlling a gate bias of the first amplifier circuit to control a gain of the first amplifier circuit; and a variable matching circuit (103) controlling a capacitor connected to the gate of the first amplifier circuit to control the gain of the first amplifier circuit. | ||||||
| 188 | Amplifier circuit | US11808256 | 2007-06-07 | US07525387B2 | 2009-04-28 | Zaman Iqbal Kazi; Junji Ito; Toshihiro Shogaki |
| An amplifier circuit includes a first bipolar transistor of which the emitter is connected to the ground, and a bias circuit of the first bipolar transistor. The bias circuit includes a second bipolar transistor constituting a current mirror circuit along with the first bipolar transistor, a first resistor connected to the bases of the first bipolar transistor and the second bipolar transistor, and a third bipolar transistor of which the emitter is connected to the bases of the first bipolar transistor and the second bipolar transistor through the first resistor, and of which the base is connected to the collector of the second bipolar transistor. The first bipolar transistor amplifies a signal input to the base thereof and then outputs the amplified signal from the collector of the first bipolar transistor. | ||||||
| 189 | CDMA power amplifier design for low and high power modes | US11784541 | 2007-04-06 | US07443236B2 | 2008-10-28 | Gee Samuel Dow; Jianwen Bao; Chun-Wen Paul Huang |
| An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels. | ||||||
| 190 | Electrical Circuit | US11815731 | 2005-02-07 | US20080143442A1 | 2008-06-19 | Erik Hemmendorff; Hakan Berg; Karin Gabrielson |
| The present invention relates to a circuit for processing a signal and comprising an amplifier (20) having an input and an output. The circuit further comprises a first switching arrangement (S3, T3) and a second switching arrangement (S2, T2). The first switching arrangement being arranged between said input and ground and said second switching arrangement being arranged between said output and ground. The switching arrangements are operatively arranged to connect said input and output to said ground so that said amplifier attenuates said signal. | ||||||
| 191 | Ground inductance compensated quadrature radio frequency amplifier | US11471836 | 2006-06-21 | US07388433B1 | 2008-06-17 | James Burr Hecht |
| The present invention is a quadrature RF amplifier including an in-phase amplifier leg and a quadrature-phase amplifier leg. The nominal gain of the in-phase amplifier leg is substantially different from the nominal gain of the quadrature-phase amplifier leg to compensate for gain imbalances introduced by the ground currents of both amplifier legs sharing a common ground lead. The gain imbalances are as a result of voltages developed across the inductance of the common ground lead. Since it is possible to completely compensate for the gain imbalances, reducing the inductance of the common ground lead may be unnecessary. | ||||||
| 192 | Constant current bias circuit and associated method | US11599932 | 2006-11-15 | US20080111629A1 | 2008-05-15 | William H. Davenport |
| A constant current bias circuit and associated method is disclosed. The constant current bias circuit comprises an output stage for amplifying a radio frequency (RF) signal, wherein the output stage is operably coupled with a voltage. The constant current bias circuit further comprises a bias circuit operably coupled with the output stage for generating a substantially constant current bias to the output stage. The constant current bias circuit still further comprises a plurality of bias transistors operably coupled with the voltage and the output stage. | ||||||
| 193 | Unilateral Feedback Power Amplifier and Method for Realizing the Same | US11621793 | 2007-01-10 | US20080068077A1 | 2008-03-20 | Zuo-Min Tsai; George D. Vendelin; Huei Wang |
| A unilateral feedback power amplifier utilizes new feedback techniques and devices to make the amplified high-frequency signal unilateral, let the output power, power gain and impedance matching simultaneously accomplish the optimal values, and enhance the stability of the system. In this feedback amplifier, a generalized multi-port feedback circuit is in shunt with the input terminal and the output terminal of the power transistor. This generalized multi-port feedback circuit receives an amplified high-frequency signal and eliminates the reverse admittance of the amplified high-frequency signal to let the admittance value of the output amplified high-frequency signal approach zero so as to be unilateral. Moreover, the generalized multi-port feedback power amplifier differs from the conventional power amplifier of cascaded architecture in that the ground terminal of the power transistor is directly connected to the system ground. Therefore, the heat-radiating problem of the power transistor can be greatly improved. | ||||||
| 194 | Power amplifier and transmitter | US11356005 | 2006-02-17 | US07336125B2 | 2008-02-26 | Irei Kyu; Shigeki Koya; Satoshi Tanaka |
| A 90-degree phase delay power divider part PSPD is connected to an input side of a carrier amplifier Amp1 and a peak amplifier Amp2, and a variable electric length power combiner VTL2 is connected to an output side thereof. A control signal Sig is applied through a control terminal Ctrl of the variable electric length power combiner VTL2, and adjustment is performed in correspondence to a carrier frequency band of a carrier signal RFs so that an electric length of the variable electric length power combiner VTL2 becomes nearly 90 degrees. As a result, an electric length of an output power combining circuit of a Doherty type amplifier can be made variable, and a power-added efficiency can be enhanced for a multi-band or broad band. | ||||||
| 195 | Low Distortion Radio Frequency (RF) Limiter | US11771106 | 2007-06-29 | US20080031382A1 | 2008-02-07 | Ichiro Aoki |
| A limiter for minimizing an amount of phase change caused by input amplitude variation includes a variable gain amplifier configured to receive a signal having an amplitude component and a phase component and having a gain controlled by a compensation capacitance and a variable resistance, in which the compensation capacitance minimizes an effect of parasitic capacitance and the variable resistance adjusts a gain in the variable gain amplifier such that the amplitude component at an output of the variable gain amplifier remains substantially constant. | ||||||
| 196 | Distributed amplifier having a variable terminal resistance | US11603222 | 2006-11-22 | US20080030278A1 | 2008-02-07 | Shih-Chieh Shin; Ming-Da Tsai; Huei Wang |
| A distributed amplifier is disclosed herein, which includes a signal amplification unit amplifying a RF input signal fed into the RF signal, a first biasing circuit providing a direct current (DC) bias signal, a second biasing circuit providing a DC bias signal, the variable terminal resistance providing an adjustable resistance, a RF signal input terminal provided for input of the RF input signal and a RF signal output terminal for output of a RF output signal. The output RF signal from the distributed amplifier is obtained from a gained version of the input RF signal. Since a load mismatch issue is compensated, a gain flatness issue is considerably improved and thus a gain-adjustable range is increased with respect to the distributed amplifier. | ||||||
| 197 | High frequency stabilization network for microwave devices and monolithic integrated circuits | US11483814 | 2006-07-10 | US20080007357A1 | 2008-01-10 | Hua Quen Tserng; Warren Robert Gaiewski; David Michael Fanning |
| A high-frequency stabilization network for microwave devices and monolithic integrated circuits. The stabilization network may comprise one or more monolithic RL parallel networks, configured to reduce in-band high-frequency oscillation, such as Gunn effect oscillation and IMPATT oscillation. | ||||||
| 198 | SEMICONDUCTOR AMPLIFIER | US11742263 | 2007-04-30 | US20070252650A1 | 2007-11-01 | Haruo KOJIMA |
| A first power source 11 for supplying a bias voltage to a gate electrode G of a field effect transistor 13, which amplifies high-frequency signals, and a second power source 15 for supplying a bias voltage to a drain electrode D of the field effect transistor 13 are provided. The protective resistance 12 is connected between the gate electrode G of the field effect transistor 13 and the first power source 11, and the bias voltage controller 14 is connected between the drain electrode D of the field effect transistor 13 and the second power source 11. Further, a voltage detector 16 is connected between both ends of the protective resistance 12 to detect a voltage drop generated between both ends of the protective resistance 12, when a rectified current flows to the gate electrode G from the drain electrode D of the field effect transistor 13. | ||||||
| 199 | PFM control circuit for DC regulator | US10908303 | 2005-05-06 | US07279869B2 | 2007-10-09 | Guang-Nan Tzeng; Yung-Chih Chen; Ya-Der Tain |
| A PFM control circuit generates a pulse control signal for controlling a switching regulator to convert an input voltage into an output voltage. The pulse control signal has a plurality of switch cycles, each of which consists of an ON-time and an OFF-time. The ON-time is applied to turn on a switching circuit of the switching regulator while the OFF-time is applied to turn off the switching circuit. A current detection signal is representative of a current flowing through an inductive device of the switching regulator. The ON-time is prolonged in accordance with an increase of a maximum of the current detection signal. A voltage detection signal is representative of the output voltage. The OFF-time is prolonged in accordance with a reduction of a falling rate of the voltage detection signal. | ||||||
| 200 | Radio frequency power amplifier | US11640866 | 2006-12-19 | US20070146077A1 | 2007-06-28 | Shingo Matsuda; Kazuki Tateoka; Hirokazu Makihara |
| A radio frequency power amplifier 1 includes a former-stage transistor 2, a latter-stage transistor 3, and an inter-stage matching circuit 4 for connecting the former-stage transistor 2 and the latter-stage transistor 3. The inter-stage matching circuit 4 includes a high-pass filter circuit including a transfer line m1, a capacitor C1 and a capacitor C2; and a transfer line m2 with which a passage phase of a secondary harmonic signal is 15 degrees or greater. | ||||||
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