| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | Audio mixing device and method, and electronic apparatus | JP2011035894 | 2011-02-22 | JP2012175427A | 2012-09-10 | IMAI YUKIHIRO |
| PROBLEM TO BE SOLVED: To provide an audio mixing device and method that implement a simpler configuration and a lower power consumption than existing techniques, and an electronic apparatus having the audio mixing device.SOLUTION: The audio mixing device includes: a digital adder for adding up a plurality of PDM signals that are respective conversions of a plurality of digital audio signals; a DA converter for DA-converting a digital audio signal output from the digital adder to output an analog audio signal; and synchronization circuits disposed prior to the digital adder to output the plurality of digital audio signals to the digital adder synchronously via the same predetermined synchronization timing clock. | ||||||
| 2 | 駆動回路及び可変利得増幅器 | JP2015207836 | 2015-10-22 | JP2017079447A | 2017-04-27 | TANAKA KEIJI |
| 【課題】広い入力範囲で動作する線形増幅器を実現すること。【解決手段】本発明の一態様に係る駆動回路12は、第1の定電流を供給するトランジスタQ5と、入力信号に応じて第1の定電流を一対の第1の電流に分流し、該一対の第1の電流の一方を第1の出力電流として出力する第1の差動対122と、入力信号に応じて第2の定電流を一対の第2の電流に分流し、該一対の第2の電流のうち第1の出力電流と逆相の電流を第2の出力電流として出力する第2の差動対123と、第1の出力電流から第2の出力電流を差し引いた電流を利得制御信号に応じて一対の第3の電流に分流する利得設定回路128と、一対の第3の電流の一方に基づき出力信号を生成する抵抗RCと、一対の第3の電流の他方に応じて第2の定電流を生成するカレントミラー回路126,127と、を有する可変利得増幅器121を備える。【選択図】図2 | ||||||
| 3 | オーディオミキシング装置及び方法並びに電子機器 | JP2011035894 | 2011-02-22 | JP5644579B2 | 2014-12-24 | 幸弘 今井 |
| 4 | MODULATOR FOR A DIGITAL AMPLIFIER | US16092883 | 2017-04-12 | US20190131999A1 | 2019-05-02 | Florian HÜHN |
| The present invention relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier.The modulator (100) comprises a pulse shaper (110) and a control unit (120) for controlling the pulse shaper (110) to convert an input signal into a bit stream (130) configured for a digital amplifier which encodes an amplitude value per clock of a carrier signal. The pulse shaper (110) can represent a respective amplitude value of the input signal with different bit patterns. The bit pattern respectively used by the pulse shaper is determined by the control unit (120) by means of a corresponding, associated control command. The modulator (100) is characterized in that in the control unit (120) an assignment (160) of the control commands to associated amplitude values resulting from amplification of the associated bit patterns with the digital amplifier (400) is stored or at least is provided in that the control unit (120) selects a control command per clock by means of the assignment (160) and the amplitude value of the input signal and drives the pulse shaper (110) accordingly. | ||||||
| 5 | TRANSIMPEDANCE AMPLIFIER WITH VARIABLE INDUCTANCE INPUT REDUCING PEAK VARIATION OVER GAIN | US15863440 | 2018-01-05 | US20180145644A1 | 2018-05-24 | Tom BROEKAERT |
| A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode. | ||||||
| 6 | LINEARIZING AND REDUCING PEAKING SIMULTANEOUSLY IN SINGLE-TO-DIFFERENTIAL WIDEBAND RADIO FREQUENCY VARIABLE GAIN TRANS-IMPEDANCE AMPLIFIER (TIA) FOR OPTICAL COMMUNICATION | US14927885 | 2015-10-30 | US20170126191A1 | 2017-05-04 | Chakravartula Nallani; Rahul Shringarpure; Georgios Asmanis; Faouzi Chaahoub; Kishan Venkataramu |
| An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier. | ||||||
| 7 | VARIABLE GAIN AMPLIFIER AND DRIVER IMPLEMENTING THE SAME | US15297892 | 2016-10-19 | US20170117863A1 | 2017-04-27 | Keiji TANAKA |
| A driver that drives an optical device, such as laser diode (LD) and/or optical modulator, is disclosed. The driver includes a variable gain amplifier (VGA) and a post amplifier. The post amplifier amplifies an output of the VGA to a preset amplifier as varying the gain of the VGA. The VGA includes two differential pairs each amplify the input signal oppositely in phases thereof and outputs of the differential pairs are compositely provided to the post amplifier. The gain of the VGA is varied by adjusting contribution of the second differential pair to the output of the VGA. | ||||||
| 8 | Audio mixing device, method thereof, and electronic device | US13371752 | 2012-02-13 | US09438362B2 | 2016-09-06 | Yukihiro Imai |
| An audio mixing device includes: an adder that adds a plurality of PDM signals each converted from a plurality of digital audio signals; a D/A converter that performs D/A conversion on a digital audio signal outputted from the adder and outputs an analog audio signal; and a synchronization device that is provided prior to the adder, and that synchronizes each of a plurality of digital signals with one another by use of the same predetermined synchronization timing signal and outputs each of them to the adder. | ||||||
| 9 | AUDIO MIXING DEVICE, METHOD THEREOF, AND ELECTRONIC DEVICE | US13371752 | 2012-02-13 | US20120213389A1 | 2012-08-23 | Yukihiro IMAI |
| An audio mixing device includes: an adder that adds a plurality of PDM signals each converted from a plurality of digital audio signals; a D/A converter that performs D/A conversion on a digital audio signal outputted from the adder and outputs an analog audio signal; and a synchronization device that is provided prior to the adder, and that synchronizes each of a plurality of digital signals with one another by use of the same predetermined synchronization timing signal and outputs each of them to the adder. | ||||||
| 10 | Apparatus and method for performing a calculation operation | US11436514 | 2006-05-19 | US07822800B2 | 2010-10-26 | Thomas Schulze; Carsten Wegner |
| The invention provides an apparatus and a method for performing a calculation operation with at least one input signal consisting of signal sections, wherein each signal section of said input signal has a constant amplitude. The apparatus comprises a signal transformation unit for transforming at least one input signal into a first intermediary signal having a virtual amplitude with respect to at least one carrier signal. The calculation unit is provided for performing the calculation operation on said first intermediary signal to generate a second intermediary signal. A signal re-transformation unit re-transforms the second intermediary signal into an output signal consisting of signal sections, wherein each signal section of said output signal has a constant amplitude. | ||||||
| 11 | Methods and apparatus for reducing peak-to-RMS amplitude ratio in communication signals | US12042689 | 2008-03-05 | US07639098B2 | 2009-12-29 | Stephen V. Schell; Richard W. D. Booth |
| A pulse amplitude modulation (PAM) signal generator that injects a copy of a pulse into the PAM baseband signal prior to frequency upconversion and power amplification. The pulse comprises a function of, or an extra copy of, a pulse in the PAM baseband signal. The pulse injector analyzes the PAM baseband signal for times when a predetermined threshold is exceeded and forms a pulse that is constructed and arranged to reduce the amplitude of the PAM baseband signal to a desired peak amplitude when the pulse is added to the PAM baseband signal. | ||||||
| 12 | Apparatus and method for performing a calculation operation | US11436514 | 2006-05-19 | US20070288541A1 | 2007-12-13 | Thomas Schulze; Carsten Wegner |
| The invention provides an apparatus and a method for performing a calculation operation with at least one input signal consisting of signal sections, wherein each signal section of said input signal has a constant amplitude. The apparatus comprises a signal transformation unit for transforming at least one input signal into a first intermediary signal having a virtual amplitude with respect to at least one carrier signal. The calculation unit is provided for performing the calculation operation on said first intermediary signal to generate a second intermediary signal. A signal re-transformation unit re-transforms the second intermediary signal into an output signal consisting of signal sections, wherein each signal section of said output signal has a constant amplitude. | ||||||
| 13 | High-efficiency RF digital power amplifier with joint duty-cycle/amplitude modulation | US15420109 | 2017-01-31 | US10135409B1 | 2018-11-20 | David Cousinard; Renaldi Winoto |
| A power amplifier includes an array of transistors having outputs that are connected in parallel to one another and coupled to an output network. The power amplifier further includes digital circuitry, configured to receive a sequence of control words that specify respective amplitudes of a signal to be transmitted in respective time intervals, and to transmit the signal by performing, for each control word and respective time interval: partitioning the control word into a Least Significant Bit (LSB) portion and a Most Significant Bit (MSB) portion; selecting a time duration based on the LSB portion; selecting an amplitude based on the MSB portion; and activating the array of transistors during the time interval in accordance with the selected time duration and the selected amplitude. | ||||||
| 14 | Variable gain amplifier and driver implementing the same | US15297892 | 2016-10-19 | US09973165B2 | 2018-05-15 | Keiji Tanaka |
| A driver that drives an optical device, such as laser diode (LD) and/or optical modulator, is disclosed. The driver includes a variable gain amplifier (VGA) and a post amplifier. The post amplifier amplifies an output of the VGA to a preset amplifier as varying the gain of the VGA. The VGA includes two differential pairs each amplify the input signal oppositely in phases thereof and outputs of the differential pairs are compositely provided to the post amplifier. The gain of the VGA is varied by adjusting contribution of the second differential pair to the output of the VGA. | ||||||
| 15 | Class D amplifier circuit | US15466661 | 2017-03-22 | US09899978B2 | 2018-02-20 | John Paul Lesso; Toru Ido |
| This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205). | ||||||
| 16 | CIRCUITS AND OPERATING METHODS THEREOF FOR CORRECTING PHASE ERRORS CAUSED BY GALLIUM NITRIDE DEVICES | US15198283 | 2016-06-30 | US20180007650A1 | 2018-01-04 | Damian McCann |
| Circuits and operating methods thereof for correcting phase errors introduced by amplifiers employing gallium nitride (GaN) transistors are described. The phase errors are caused by trapping effects exhibited by the GaN transistors. The circuits described herein pre-distort the phase of the input signal to compensate for the phase error introduced by the amplifier. Thereby, the phase of the output signal of the amplifier has a reduced phase error. For example, the output signal may have a near zero (or zero) phase error. | ||||||
| 17 | Linearizing and reducing peaking simultaneously in single-to-differential wideband radio frequency variable gain trans-impedance amplifier (TIA) for optical communication | US14927885 | 2015-10-30 | US09787272B2 | 2017-10-10 | Chakravartula Nallani; Rahul Shringarpure; Georgios Asmanis; Faouzi Chaahoub; Kishan Venkataramu |
| An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier. | ||||||
| 18 | Transimpedance amplifier with variable inductance input reducing peak variation over gain | US15226814 | 2016-08-02 | US09774305B1 | 2017-09-26 | Tom Broekaert |
| A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode. | ||||||
| 19 | CLASS D AMPLIFIER CIRCUIT | US15466661 | 2017-03-22 | US20170194926A1 | 2017-07-06 | John Paul LESSO; Toru IDO |
| This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205). | ||||||
| 20 | Class D amplifier circuit | US14836006 | 2015-08-26 | US09628040B2 | 2017-04-18 | John Paul Lesso; Toru Ido |
| This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205). | ||||||
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