| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | DOHERTY AMPLIFIER | US15772133 | 2016-01-05 | US20180287566A1 | 2018-10-04 | Yuji KOMATSUZAKI; Shintaro SHINJO; Keigo NAKATANI; Takaaki YOSHIOKA |
| A Wilkinson power divider includes: π-type LPFs connected to an input terminal; a T-type HPF having one end connected to one of the π-type LPFs and having another end connected to a carrier amplifier; another T-type HPF having one end connected to another one of the π-type LPFs and having another end connected to a λ/4 line; and an isolation resistor connected to connection points. | ||||||
| 82 | MULTI-MODE POWER AMPLIFIER | US15865194 | 2018-01-08 | US20180234061A1 | 2018-08-16 | Ying Shi; Jinghang Feng |
| A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit. | ||||||
| 83 | Fast settling capacitive gain amplifier circuit | US15600484 | 2017-05-19 | US10044327B2 | 2018-08-07 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 84 | POWER AMPLIFIER AND RADIO TRANSMITTER | US15580724 | 2015-06-15 | US20180167042A1 | 2018-06-14 | Toshiyuki NAGASAKU |
| A power amplifier includes a carrier amplifier that operates from when an input signal is small, a peak amplifier that starts to operate when the input signal becomes large, a phase adjusting circuit that adjusts phases of an output of the carrier amplifier and an output of the peak amplifier, an impedance transforming line that transforms a load of the carrier amplifier when the input signal is small, and has a characteristic impedance close to an optimum load impedance of the carrier amplifier, and a circuit that is arranged between the output of the carrier amplifier and the impedance transforming line and reduces an output capacitance of the carrier amplifier. | ||||||
| 85 | Operational Amplifier and Differential Amplifying Circuit Thereof | US15818547 | 2017-11-20 | US20180152156A1 | 2018-05-31 | KUAN-YU SHIH |
| An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough. | ||||||
| 86 | Passive acoustic resonator based RF receiver | US15415538 | 2017-01-25 | US09966981B2 | 2018-05-08 | Dirk Robert Walter Leipold; George Maxim; Baker Scott |
| A radio frequency (RF) receiver, which has an RF filter and impedance matching circuit and an RF low noise amplifier (LNA), is disclosed. The RF filter and impedance matching circuit includes a first passive RF acoustic resonator; provides an RF bandpass filter having an RF receive band based on the first passive RF acoustic resonator; and presents an input impedance at an RF input and an output impedance at an RF output, such that a ratio of the output impedance to the input impedance is greater than 40. The RF LNA is coupled to the RF output. | ||||||
| 87 | Weakly coupled tunable RF receiver architecture | US15587581 | 2017-05-05 | US09954498B2 | 2018-04-24 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal. | ||||||
| 88 | FAST SETTLING CAPACITIVE GAIN AMPLIFIER CIRCUIT | US15600484 | 2017-05-19 | US20180076779A1 | 2018-03-15 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 89 | POWER TRANSISTOR WITH HARMONIC CONTROL | US15674368 | 2017-08-10 | US20180061785A1 | 2018-03-01 | Pascal Peyrot; Olivier Lembeye; Sai Sunil Mangaonkar |
| A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different. | ||||||
| 90 | Advanced 3D inductor structures with confined magnetic field | US14450156 | 2014-08-01 | US09899133B2 | 2018-02-20 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components. | ||||||
| 91 | Multi-mode power amplifier | US14975621 | 2015-12-18 | US09887669B2 | 2018-02-06 | Ying Shi; Jinghang Feng |
| A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit. | ||||||
| 92 | INVERTER FOR INDUCTIVE POWER TRANSFER | US15548172 | 2016-02-02 | US20180034383A1 | 2018-02-01 | Samer ALDHAHER; Manuel PINUELA RANGEL; Paul David MITCHESON; David Christopher YATES |
| An inverter for inductive power transfer is disclosed. The inverter comprises a first inductor and a switching element in series between power supply terminals, the switching element being operable to be switched at a first frequency; a first capacitance in parallel with the switching element between the first inductor and a power supply terminal; a first tank circuit in parallel with the first capacitance, the first tank circuit comprising a second inductor and a second capacitance, wherein the second capacitance is arranged in series with the second inductor; a second tank circuit in parallel with the first capacitance; and a third capacitance in series with the first inductor between the first tank circuit and the second tank circuit, wherein the second tank circuit comprises a transmitter coil and a fourth capacitance, the fourth capacitance being arranged in parallel or series with the transmitter coil; wherein the fourth capacitance is selected such that the resonant frequency of the second tank circuit is not equal to the first frequency, and wherein the second inductor and the second capacitance are selected such that the resonant frequency of the first tank circuit is an integer multiple, greater than one, of the first frequency. | ||||||
| 93 | ADVANCED 3D INDUCTOR STRUCTURES WITH CONFINED MAGNETIC FIELD | US15717525 | 2017-09-27 | US20180019045A1 | 2018-01-18 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components. | ||||||
| 94 | Tunable RF filter based RF communications system | US14298863 | 2014-06-06 | US09866197B2 | 2018-01-09 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| RF communications circuitry, which includes a first RF filter structure, is disclosed. The first RF filter structure includes a first tunable RF filter path and a second tunable RF filter path. The first tunable RF filter path includes a pair of weakly coupled resonators. Additionally, a first filter parameter of the first tunable RF filter path is tuned based on a first filter control signal. A first filter parameter of the second tunable RF filter path is tuned based on a second filter control signal. | ||||||
| 95 | Weakly coupled tunable RF transmitter architecture | US14450204 | 2014-08-01 | US09825656B2 | 2017-11-21 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| RF communications circuitry, which includes a first tunable RF filter and an RF power amplifier (PA), is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The RF PA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal. | ||||||
| 96 | FRONT-END AMPLIFIER CIRCUITS FOR BIOMEDICAL ELECTRONICS | US15383261 | 2016-12-19 | US20170272036A1 | 2017-09-21 | Chung-Yu WU; Ya-Syuan SUNG |
| A front-end amplifier circuit for receiving a biological signal includes a signal channel. The signal channel amplifies the biological signal to generate a detection current and includes a capacitive-coupled transconductance amplifier. The capacitive-coupled transconductance amplifier amplifies the biological signal with a transconductance gain to generate a first current. | ||||||
| 97 | VSWR detector for a tunable filter structure | US14450028 | 2014-08-01 | US09755671B2 | 2017-09-05 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| Embodiments of radio frequency (RF) filter front-end circuitry are disclosed that include a tunable RF filter structure having weakly coupled resonators and a Voltage Standing Wave Ratio (VSWR) control circuit. The VSWR control circuit is configured to detect a VSWR at a terminal of the tunable RF filter structure and to dynamically tune the tunable RF filter structure based on the VSWR. In this manner, the VSWR control circuit tunes the tunable RF filter structure to improve performance of tunable RF filter structure over variations in the VSWR. | ||||||
| 98 | WEAKLY COUPLED TUNABLE RF RECEIVER ARCHITECTURE | US15587581 | 2017-05-05 | US20170237404A1 | 2017-08-17 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal. | ||||||
| 99 | Weakly coupled tunable RF receiver architecture | US14450199 | 2014-08-01 | US09705478B2 | 2017-07-11 | George Maxim; Dirk Robert Walter Leipold; Baker Scott |
| RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal. | ||||||
| 100 | Inverse class F amplifiers with intrinsic capacitance compensation | US15068348 | 2016-03-11 | US09692373B2 | 2017-06-27 | Joseph Staudinger; Maruf Ahmed; Hussain H. Ladhani |
| The embodiments described herein provide inverse class F (class F−1) amplifiers. In general, the inverse class F amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class F voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. Specifically, the transistor is configured with the output inductance and transmission line to form a parallel LC circuit that resonates at the second harmonic frequency. The parallel LC circuit effectively creates high impedance for the second harmonic signals, thus blocking the capacitive reactance path to ground for those harmonic signals that the intrinsic output capacitance would otherwise provide. This facilitates the operation of the amplifier as an effective, high efficiency, inverse class F amplifier. | ||||||
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