| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | Spur cancellation in GSM-GPRS-EDGE power amplifiers with DC-DC converters | US14067548 | 2013-10-30 | US09065385B2 | 2015-06-23 | Oleksandr Gorbachov |
| A radio frequency (RF) power amplifier circuit with spur cancellation for GSM/GPRS/EDGE transceivers is disclosed. There is a power amplifier with an RF input, an RF output, and a voltage supply input. Additionally, there is an adjustable DC-DC converter with an input connected to a battery, an output connected to the voltage supply input of the power amplifier with a DC supply voltage signal generated thereby. A spur compensator generates an error control signal responsive to spurs in the DC supply voltage signal. The error control signal is applied to the RF input of the power amplifier. | ||||||
| 62 | RF pulse signal generation switching circuit, RF pulse signal generating circuit, and target object detecting apparatus | US13648579 | 2012-10-10 | US08994579B2 | 2015-03-31 | Tomonao Kobayashi |
| An RF pulse signal generation switching circuit for controlling an output of a power FET for amplifying a high frequency signal to generate an RF pulse signal that is the high frequency signal pulse formed into a pulse-wave shape is provided. The circuit includes first and third n-type FETs of which gates are inputted with a control pulse that supplies a rise timing and a fall timing of a pulse, and a second n-type FET of which a gate is connected with a drain of the first FET. A source of the first FET and a source of the third FET are grounded, respectively. The drain of the first FET is applied with a first drive voltage via a resistor. A drain of the second FET is applied with a second drive voltage. A source of the second FET is connected with a drain of the third FET and the connection point therebetween is connected with the power FET. A capacitor is connected between the connection point and an end of the resistor from which the first drive voltage is applied. | ||||||
| 63 | SPUR CANCELLATION IN GSM-GPRS-EDGE POWER AMPLIFIERS WITH DC-DC CONVERTERS | US14067548 | 2013-10-30 | US20140118075A1 | 2014-05-01 | OLEKSANDR GORBACHOV |
| A radio frequency (RF) power amplifier circuit with spur cancellation for GSM/GPRS/EDGE transceivers is disclosed. There is a power amplifier with an RF input, an RF output, and a voltage supply input. Additionally, there is an adjustable DC-DC converter with an input connected to a battery, an output connected to the voltage supply input of the power amplifier with a DC supply voltage signal generated thereby. A spur compensator generates an error control signal responsive to spurs in the DC supply voltage signal. The error control signal is applied to the RF input of the power amplifier. | ||||||
| 64 | Protection circuit for radio frequency power amplifier | US13115024 | 2011-05-24 | US08487705B2 | 2013-07-16 | Jingshi Yao; Peter Hu; Xiaopeng Sun; Barry Jia-Fu Lin; Mehra Mokalla |
| Embodiments of circuits, apparatuses, and systems for a protection circuit to protect against overdrive or overvoltage conditions. Other embodiments may be described and claimed. | ||||||
| 65 | PROTECTION CIRCUIT FOR RADIO FREQUENCY POWER AMPLIFIER | US13115024 | 2011-05-24 | US20110292554A1 | 2011-12-01 | Jingshi Yao; Peter Hu; Xiaopeng Sun; Barry Jia-Fu Lin; Mehra Mokalla |
| Embodiments of circuits, apparatuses, and systems for a protection circuit to protect against overdrive or overvoltage conditions. Other embodiments may be described and claimed. | ||||||
| 66 | Amplifier circuit | US12058450 | 2008-03-28 | US07612611B2 | 2009-11-03 | Andreas Loth |
| An amplifier circuit for amplifying a high-frequency input signal comprises an amplifier stage, which amplifies the high-frequency input signal as a function of an operating point of the amplifier stage and generates an operating point-dependent signal, an observer stage, which replicates the amplifier stage and generates an observation signal, a regulator, which is supplied with the operating point-dependent signal and the observation signal, and an control element, which influences the operating point of the amplifier stage and is driven by the regulator, whereby the regulator drives the control element in such a way that the operating point of the amplifier stage is substantially independent of a level of the high-frequency input signal. | ||||||
| 67 | Amplifier feedback and bias configuration | US11518109 | 2006-09-08 | US20080061884A1 | 2008-03-13 | Robert Michael Fisher; Michael L. Hageman |
| A wireless communication device output amplifier configured to reduce or eliminate out of band oscillations from voltage standing waves generated by antenna impedance mismatch reflection. The amplifier is configured with an input, output, and biasing node. The biasing node is configured to receive a biasing signal from a biasing amplifier. The biasing amplifier draws current from the biasing node while providing the biasing voltage to the output amplifier. To reduce or eliminate out of band voltage standing waves from antenna reflections, a frequency dependant network is provided as a feedback loop to selectively provide feedback to the output amplifier to reduce or eliminate unwanted out of band oscillations, such as voltage standing waves. The frequency dependant network may comprise one or more resistors, inductors, and capacitors which are of small size and may be integrated. | ||||||
| 68 | Series fed amplified antenna reflect array | US11508085 | 2006-08-22 | US07298344B2 | 2007-11-20 | Kenneth W. Brown |
| A reflect array antenna. The array includes a plurality of unit cells. Each cell includes a first dipole antenna having a first orientation and a first polarization; a second dipole antenna having a second orientation and a second polarization; and an amplifier input coupled inline to said first dipole antenna and output coupled inline to said second dipole antenna. The array further includes N first dipole antennas having a first orientation and a first polarization; M second dipole antennas having a second orientation and a second polarization; and a plurality of unit cells, each cell including an amplifier input coupled inline to a first dipole antenna and output coupled inline to a second dipole antenna. The second orientation and the second polarization are orthogonal to the first orientation and the first polarization. Each amplifier includes a transistor with an input terminal and first and second output terminals. Each input terminal is connected to the first dipole antenna and the output terminals are coupled to the second dipole antenna. The first and second terminals are adapted to be coupled to second and first terminals respectively of a neighboring cell in the array. A direct current bias for the array is applied via the second dipole antenna. Input bias for the transistors is applied via the first dipole antenna. A unique gate bias voltage for each transistor in the array is provided on a row-by-row basis via a voltage divider network. The voltage divider network includes (N−1) first resistors Rb connected in series to a first source of supply potential, where N is the number of rows in the array. Each of the resistors is connected to provide an input voltage to one of the transistors in the array. The resistive network further includes M second resistors RL connected to a respective one of the second dipoles antennas, where M is the number of columns in the array. The array is fabricated by via a metallization pattern which is disposed on a first substrate to provide a chip. The chip is secured to a second substrate with a bonding agent. In the best mode, the bonding agent is an anisotropic electrically conductive bonding film that allows current to flow along a path orthogonal to a surface of the array while blocking current flow parallel to the surface of the array. | ||||||
| 69 | Amplifier device | US759123 | 1977-01-13 | US4121169A | 1978-10-17 | Masayuki Iwamatsu |
| An amplifier device comprises a pair of cascode connected transistors wherein the base of the first transistor is connected to an input terminal, the emitter is grounded through a resistor, the collector is connected to the emitter of the second transistor, the collector of the second transistor is connected to a source through a resistor and to an output terminal, and the base of the second transistor is connected to the emitter of the first transistor via a biasing circuitry. The voltage drop between the collector and the emitter of the first transistor is kept constant irrespective of the input signal voltage. The amplifier operates stably with a small deformation of the waveform. | ||||||
| 70 | Apparatus for Radio-Frequency Receiver with Reduced Power Consumption and Associated Methods | US15609412 | 2017-05-31 | US20180351593A1 | 2018-12-06 | Navin Harwalkar; Arup Mukherji; John M. Khoury |
| An apparatus includes a radio-frequency (RF) receiver. The RF receiver includes a single-balanced passive mixer driven by the output of a low noise amplifier (LNA) and a passive filter driven by an output of the single-balanced passive mixer. The RF receiver further includes a programmable gain amplifier (PGA) having an input resistance that generates noise, where the PGA is driven by an output of the passive filter, and the noise generated by the input resistance of the PGA is suppressed. | ||||||
| 71 | Integrated gallium nitride power amplifier and switch | US15487112 | 2017-04-13 | US10103696B1 | 2018-10-16 | James E. Mitzlaff |
| A multi-band RF power amplifier circuit fabricated using GaN technology includes a RF power amplifier coupled to a multi-band RF switch without an intervening impedance matching network between the RF power amplifier and the multi-band RF switch. The multi-band RF switch includes a plurality of Unit HEMT cells. In one IC package, the RF power amplifier, the multi-band RF switch, a controller for controlling the switch and all connection therebetween are totally contained within the IC package. In another IC package, the RF power amplifier and the multi-band RF switch are disposed on a single substrate. | ||||||
| 72 | BIAS CIRCUIT | US15839189 | 2017-12-12 | US20180275709A1 | 2018-09-27 | Chih-Sheng Chen; Tien-Yun Peng; Jhao-Yi Lin |
| A bias circuit includes a first transistor, a second transistor, a first resistor and a second resistor. The first end of the first transistor is coupled to a first voltage source. One end of the first resistor is coupled to the second end of the first transistor, and the other end of the first resistor is coupled to the control terminal of the first transistor. The first end of the second transistor is coupled to a second voltage source, and the second end of the second transistor is coupled to the control terminal of the first transistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor is coupled to the control terminal of the second transistor. | ||||||
| 73 | AMPLIFIER WITH NONLINEARITY COMPENSATION | US15986527 | 2018-05-22 | US20180269839A1 | 2018-09-20 | Arash Mehrabi; Zongyu Dong; Vijayakumar Dhanasekaran; Dongyang Tang; Chien-Chung Yang |
| An apparatus includes a reference voltage circuit having a bandgap input and a reference voltage output. The apparatus also includes a digital-to-analog converter (DAC) coupled to the reference voltage output and having a digital signal input. The apparatus includes an amplifier having a first input coupled to an output of the DAC. The first input is coupled to an output of the amplifier via a feedback resistor. The apparatus includes a resistor coupled to the reference voltage output and having a body terminal coupled to the output of the amplifier. | ||||||
| 74 | Positive Temperature Coefficient Bias Compensation Circuit | US15908469 | 2018-02-28 | US20180262166A1 | 2018-09-13 | Tsuyoshi Takagi; Tero Tapio Ranta; Keith Bargroff; Christopher C. Murphy; Robert Mark Englekirk |
| Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. Other embodiments include bias compensation circuits that directly regulate a bias signal to an amplifier stage as a function of localized heating of one or more of amplifier stages. Such bias compensation circuits include physical placement of at least one bias compensation circuit element in closer proximity to at least one amplifier stage than other bias compensation circuit elements. One bias compensation circuit embodiment includes a temperature-sensitive current mirror circuit for regulating the bias signal. Another bias compensation circuit embodiment includes a temperature-sensitive element having a positive temperature coefficient (PTC) for regulating the bias signal. | ||||||
| 75 | Method and device for self-biased and self-regulated common-mode amplification | US15589814 | 2017-05-08 | US10063189B2 | 2018-08-28 | Michel Ayraud; Sandrine Nicolas |
| An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor. | ||||||
| 76 | Systems and methods providing an intermodulation distortion sink | US15472055 | 2017-03-28 | US10014845B2 | 2018-07-03 | Timothy Donald Gathman; Chirag Dipak Patel; Sasha Vujcic; Aleksandar Miodrag Tasic; Wu-Hsin Chen; Klaas van Zalinge |
| A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node. | ||||||
| 77 | LNA with Programmable Linearity | US15895863 | 2018-02-13 | US20180175807A1 | 2018-06-21 | Hossein Noori; Chih-Chieh Cheng |
| A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention. | ||||||
| 78 | Amplifier with nonlinearity compensation | US15188364 | 2016-06-21 | US09998077B2 | 2018-06-12 | Arash Mehrabi; Zongyu Dong; Vijayakumar Dhanasekaran; Dongyang Tang; Chien-Chung Yang |
| An apparatus includes an amplifier having a first input and a second input. A first feedback resistor is coupled to the first input and has a first body terminal coupled to a first bias terminal. A second feedback resistor is coupled to the second input and has a second body terminal coupled to a second bias terminal. | ||||||
| 79 | ADAPTIVE MULTIBAND POWER AMPLIFIER APPARATUS | US15719843 | 2017-09-29 | US20180123529A1 | 2018-05-03 | Byeong Hak JO; Jong Ok HA; Jeong Hoon KIM; Youn Suk KIM |
| A power amplifier apparatus, includes an envelope tracking (ET) current bias circuit configured to generate a first ET bias current by calculating a direct current DC, based on a reference voltage, and an ET current, based on an ET voltage, according to an envelope of an input signal; and a power amplifier circuit having a bipolar junction transistor supplied with the first ET bias current and a power voltage to amplify the input signal, wherein an average current of the first ET bias current is controlled to be substantially constant. | ||||||
| 80 | Power amplifier circuit | US15409506 | 2017-01-18 | US09935583B2 | 2018-04-03 | Takayuki Abe; Junji Sato |
| A power amplifier circuit includes an input that receives a first input signal having a first phase and a second input signal having a second phase, a first transistor that includes a source that is supplied with a first voltage, and a gate that receives the first input signal, a second transistor that includes a source that is supplied with the first voltage, and a gate that receives the second input signal, a first neutralizing circuit that neutralizes a parasitic element, a second neutralizing circuit that neutralizes a parasitic element, N third transistors, N being an integer equal to or higher that 1, N fourth transistors, and an output that is connected between a drain of the N-th third transistor and a drain of the N-th fourth transistor and outputs a first output signal having a third phase and a second output signal having a fourth phase. | ||||||
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