| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 用于人造卫星上装载的微波设备的电子装置 | CN200880127430.2 | 2008-12-16 | CN101953066A | 2011-01-19 | C·伊贝尔; C·德巴尔热 |
| 本发明提供关于微波链路的传导敏感度的规格参数的保持与改进的解决方案。本发明的主要优点是能够通过简单的在不呈现显著的传导敏感度性能的单元(CRF1，CRF2)之间增加一个或多个180°移相器(PHI)，来显著地衰减例如集成到人造卫星中的微波装置的微波链路中携带的寄生调制信号(PAR4)。因此，本发明能够省略用于衰减寄生信号的，通常集成在所有现有微波设备中出现的电源和其他DC/DC转换器(ALIM1)中的某些元件。 | ||||||
| 2 | METHODS AND CIRCUITRY TO TRIM COMMON MODE TRANSIENT CONTROL CIRCUITRY | US15414920 | 2017-01-25 | US20170133986A1 | 2017-05-11 | Anthony B. Candage |
| Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | ||||||
| 3 | Power amplifiers coupled in series | US14589128 | 2015-01-05 | US09520843B2 | 2016-12-13 | Lars Arknaes-Pedersen |
| A power amplifier system is disclosed, the power amplifier system comprising two power supplies, four amplifier half-bridges arranged as two amplifier full bridges, and an audio processor for establishing control signals for the amplifier full-bridges, where the audio processor and one of the power supplies share a common ground potential, whereas the other power supply has a floating ground; wherein both the amplifier with common ground and the amplifier with floating ground have an amplifier interconnection output and an amplifier output, and wherein the amplifier interconnection outputs are connected, and a load is connected to the amplifier outputs. Further are disclosed amplification methods and PA systems correspondingly. | ||||||
| 4 | COMMUNICATION OVER A VOLTAGE ISOLATION BARRIER | US14836424 | 2015-08-26 | US20160065398A1 | 2016-03-03 | Anthony B. Candage; Aswath Krishnan Krishnamoorthy |
| A transmitter circuit comprises: an input, an encoder circuit, and a transmitter. During operation, the transmitter circuit receives an input signal. The encoder circuit encodes the received input signal into an encoded signal. The encoder circuit produces the encoded signal: i) to indicate changing states of the input signal, and ii) to include a supplemental transient signal with respect to the received input signal. The transmitter transmits the encoded signal from an output of the first circuit over a link to a second circuit such as a receiver circuit. A receiver decodes the encoded signal to reproduce a rendition of the input signal to control remote power supply circuitry. Presence of the supplemental transient signal in the encoded signal indicates to the receiver circuit that the first circuit actively transmits the output signal even though there may not be any change to a current state of the input signal. | ||||||
| 5 | Circuit arrangement with a multiplexer | US686196 | 1996-07-24 | US5864561A | 1999-01-26 | Erwin Becher |
| To connect one out of N signal channels (K.sub.1, K.sub.2, K.sub.N) each having a signal line (L.sub.1, L.sub.2, L.sub.N) and a channel zero line (N.sub.1, N.sub.2, N.sub.N), where N is greater than one, to one input of a (differential) amplifier (1) whose circuit is referenced to an associated ground (SN), a one-out-of-N multiplexer (2) is provided having 3N switching paths (S.sub.11, S.sub.21, S.sub.31, S.sub.12, S.sub.22, S.sub.32, S.sub.1N, S.sub.2N, S.sub.3N), a first (S.sub.11, S.sub.12, S.sub.1N) of which serves to connect the N signal lines (L.sub.1, L.sub.2, L.sub.N) to said input, and a second (S.sub.21, S.sub.22, S.sub.2N) of which serves to advance the N channel zero lines (N.sub.1, N.sub.2, N.sub.N). The respective inputs of the switching paths of a third switching-path set (S.sub.31, S.sub.32, S.sub.N) are connected to the respective inputs of the switching paths of the second switching-path set (S.sub.21, S.sub.22, S.sub.2N), and the outputs of the latter are commoned to one input of an auxiliary (differential) amplifier (3). The outputs of the third switching-path set (S.sub.31, S.sub.23, S.sub.2N) are commoned to the output of the auxiliary (differential) amplifier, whose circuit is referenced to the ground (SN) of the (differential) amplifier (1). | ||||||
| 6 | Amplifier for cancelling noise between circuit systems | US848269 | 1997-04-29 | US5841308A | 1998-11-24 | Mitsuru Nagata |
| A reference potential difference canceling circuit is provided in a circuit system of a transmitter side to remove noise caused by impedance Z between circuit systems having different reference potentials from a signal, and to transmit the signal. The reference potential of the circuit system of a receiver side is supplied to an input terminal of the reference potential difference canceling circuit, and its output terminal is connected to an input terminal of an output amplifier to which a transmitting signal is input. A gain of the reference potential difference canceling circuit is set to a reciprocal number of a gain of the output amplifier. | ||||||
| 7 | AMPLIFYING DEVICE | US16217542 | 2018-12-12 | US20190191250A1 | 2019-06-20 | Shinichi FUJITA |
| An amplifying device includes first and second substrates. The first substrate has a first mounting surface, and the second substrate has a second mounting surface. The first mounting surface of the first substrate that is opposite the second substrate is provided with: a first ground line; a first signal line configured to transfer an audio signal; and a first amplifier configured to amplify the audio signal. The second mounting surface of the second substrate that is opposite the first substrate is provided with: a second grounded line; a second signal line configured to transfer an audio signal; and a second amplifier configured to amplify the audio signal. The first and second grounded lines correspond to each other in position and shape, and overlap in planar view. The first and second signal lines correspond to each other in position and shape, and overlap in planar view. | ||||||
| 8 | Methods and circuitry to trim common mode transient control circuitry | US15414920 | 2017-01-25 | US09998076B2 | 2018-06-12 | Anthony B. Candage |
| Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | ||||||
| 9 | Driver integrated circuit | US14122623 | 2012-05-24 | US09698783B2 | 2017-07-04 | Wen Li; Norio Chujo; Masami Makuuchi; Takehito Kamimura |
| Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2). | ||||||
| 10 | Methods and circuitry to trim common mode transient control circuitry | US14835973 | 2015-08-26 | US09621123B2 | 2017-04-11 | Anthony B. Candage |
| Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | ||||||
| 11 | HEADSET AMPLIFICATION CIRCUIT WITH ERROR VOLTAGE SUPPRESSION | US14506062 | 2014-10-03 | US20160100243A1 | 2016-04-07 | Ulrik Sørensen Wismar; Sejun Kim |
| A headset driver circuit is described which comprises a connector interface. The connector interface comprises a first terminal, a second terminal and a third terminal for establishing respective electrical connections to a first speaker, a microphone and a common ground node of a headphone, earphone or headset, respectively. A first power amplifier is coupled to the first terminal to supply a first audio output signal to the first speaker of the headset. A first switch arrangement comprises a first ground switch is configured for selectively connecting and disconnecting the second terminal and a ground node of the headset driver circuit. The headset driver circuit further comprises a second ground switch configured for selectively connecting and disconnecting the third terminal and the ground node. The headset driver circuit also comprises a differential preamplifier, e.g. a microphone preamplifier, configured to generate a microphone output voltage where the differential preamplifier comprises a first signal input coupled to the second terminal and a second signal input coupled to the third terminal of the connector interface. An error suppression circuit is configured to sense or sample a noise or error voltage at the second terminal when ground connected or the third terminal when ground connected. The error suppression circuit is further configured to add the sensed or sampled noise or error voltage to a predetermined DC bias voltage and generate an error compensated DC bias voltage for the ungrounded one of the second and third terminals of the connector interface. | ||||||
| 12 | ELECTRONIC DEVICE FOR MICROWAVE APPARATUSES ONBOARD A SATELLITE | US12919219 | 2008-12-16 | US20100327933A1 | 2010-12-30 | Christophe Ibert; Cecile Debarge |
| The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment. | ||||||
| 13 | Differential audio line receiver | JP52001896 | 1995-12-22 | JP4310383B2 | 2009-08-05 | イー． ホイトロック，ウィリアム |
| 14 | Circuit arrangement comprising a multiplexer | JP19805796 | 1996-07-26 | JP3091138B2 | 2000-09-25 | ベーヒャー エルヴィン |
| 15 | Driver integrated circuit | JP2011119185 | 2011-05-27 | JP5473986B2 | 2014-04-16 | ウェン 李; 徳男 中條; 雅巳 幕内; 勇仁 上村 |
| Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2). | ||||||
| 16 | Amplifier circuit | JP12464996 | 1996-05-20 | JP3410901B2 | 2003-05-26 | 満 永田 |
| 17 | Circuit device provided with multiplexer | JP19805796 | 1996-07-26 | JPH0951234A | 1997-02-18 | ERUBUIN BEEHIYAA |
| PROBLEM TO BE SOLVED: To ensure zero point offset by providing 1st, 2nd, 3rd switching period sets and connecting the 2nd and 3rd switching period sets to an auxiliary amplifier to relate even the auxiliary amplifier to a zero point of an amplifier. SOLUTION: First switching period sets S11 , S12 S1 N connect N-sets of signal channels L1 , L2 , LN to one input of an amplifier 1 so as to relate the amplifier 1 to a circuit zero point SN. Second switching period sets S21 , S22 , S2 N are used to connect further N-sets of channel zero point lines N1 , N2 , Nn . Thus, inputs of third switching period sets S31 , S32 , S3n connected to inputs of the sets S21 , S22 , S2n and outputs are connected in common to an auxiliary amplifier 3. The amplifier 3 is related to the circuit zero point SN similarly to the amplifier. The potential at the zero point SN of a 1-out-of-N multiplexer 2 is applied to each multiplexer of the lines N1 , N2 , Nn . | ||||||
| 18 | DISPOSITIF ELECTRONIQUE DESTINE A DES EQUIPEMENTS HYPERFREQUENCES EMBARQUES SUR SATELLITE | EP08872901.7 | 2008-12-16 | EP2248254A1 | 2010-11-10 | IBERT, Christophe; DEBARGE, Cécile |
| The present invention provides a solution for maintaining and improving the specifications of the conducted susceptibility of a microwave channel. The main advantage of the invention is to provide a significant attenuation of the parasite modulated signals (PAR4) conveyed in the microwave channels of microwave devices such as those integrated into satellites, by simply adding one or more 180° phase shifters (PHI) between the components (CRF1,CRF2) that do not have a sufficient conducted susceptibility performance. Consequently, the invention makes it possible to omit certain elements in charge of attenuating parasitic signals and generally integrated in the power supplies and other DC/DC converters (ALIM1) present in all current microwave apparatuses. | ||||||
| 19 | Schaltungsanordnung mit einem Multiplexer | EP95112054.2 | 1995-07-29 | EP0757436B1 | 1999-12-08 | Becher, Erwin, Dipl.-Ing. (FH) |
| 20 | Driver integrated circuit | JP2011119185 | 2011-05-27 | JP2012249078A | 2012-12-13 | RI UEN; NAKAJO TOKUO; MAKUUCHI MASAMI; KAMIMURA YUHITO |
| PROBLEM TO BE SOLVED: To provide a configuration of a driver integrated circuit which is capable of outputting a voltage that exceeds the breakdown voltage of a process and satisfies required device performance (high-speed/high-voltage).SOLUTION: A differential input circuit, a level-shifting circuit, and an output circuit are manufactured using the same process, and are placed so as to be divided among 3 or more chips having different substrate potentials (sub-potentials). By setting the substrate applied voltage of the chips so as to be different from one another, an output voltage which is larger than the process breakdown voltage is provided. | ||||||
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