| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | Electronic device for microwave equipment to be mounted on an artificial satellite | JP2010547971 | 2008-12-16 | JP2011514061A | 2011-04-28 | イベール、クリストフ; デバージ、セシル |
| The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment. | ||||||
| 22 | Differential audio line receiver | JP52001896 | 1995-12-22 | JPH10511517A | 1998-11-04 | イー． ホイトロック，ウィリアム |
| (57)【要約】 差動モードの入力信号を第１および第２差動線から受信して単端信号を出力線に出力する、ブートストラップされたオーディオ線受信器。 この線受信器は、差動増幅器と、差動出力端子と差動入力端子を持つ入力増幅器を備える。 入力増幅器は差動線と差動増幅器の間に接続する。 入力増幅器は接地端子への電流路を形成し、オーディオ周波数のＡＣ信号に対して高い入力インピーダンスを保持する。 また入力増幅器はｒｆフィルタを備え、オーディオ周波数で線受信器のコモンモード雑音除去に悪影響を与えることなく、ｒｆ雑音を除去する。 一実施態様では、入力増幅器は、単位ゲインの２個の演算増幅器を備え、また入力増幅器の各入力端子と接地端子の間に２個のバイアス抵抗器を直列に接続する。 直列に接続するバイアス抵抗器の各組の間のノードと各演算増幅器の出力との間にコンデンサを接続することにより、バイアス抵抗器が低インピーダンスになって線受信器のコモンモード除去比を大きく低下させることがないようにする。 このようにして、この線受信器は広範囲の均衡および不均衡のソースインピーダンスに耐えて、線受信器のコモンモード除去比の低下を最小限にする。 | ||||||
| 23 | Amplifier circuit | JP12464996 | 1996-05-20 | JPH09312525A | 1997-12-02 | NAGATA MITSURU |
| PROBLEM TO BE SOLVED: To reduce an occupied are of a circuit by employing an analog amplifier and a simple reference voltage cancel circuit so as to eliminate the need for transmission/reception of a signal in a form of a differential signal thereby eliminating the need for an amplifier to generate a differential signal and an amplifier receiving a differential signal. SOLUTION: In a circuit system 1, a signal ei1 is fed to an input terminal of an analog amplifier 1 whose gain is A and its output is given to a circuit system 2. Suppose that no reference voltage cancel circuit 3 is employed, then an input to an analog amplifier 2 in the circuit system 2 is AXei1+Vx with respect to a reference level 2 of the circuit system 2 and then a difference Vx of the reference voltage between the two circuit systems is inputted to the circuit system 2. Thus, the reference voltage cancel circuit 3 is provided to the circuit system 1, its input terminal connects to the point of the reference level 2 of the circuit system 2, and the output of the reference voltage cancel circuit 3 is fed to the analog amplifier 1 together with another input ei1. The output of the amplifier 1 is AXei1+A×(1/A)×(-Vx) and then the noise component Vx of the reference voltage between the two circuit systems is eliminated. | ||||||
| 24 | POWER AMPLIFIER SYSTEMS WITH DIFFERENTIAL GROUND | US15698488 | 2017-09-07 | US20180076770A1 | 2018-03-15 | Foad Arfaei Malekzadeh; Stephen Joseph Kovacic |
| Apparatus and methods for power amplifier systems with differential ground are provided. In certain implementations, a semiconductor die for a radio frequency communication system includes a differential ground network configured to distribute a ground voltage. The differential ground network is substantially symmetric with respect to a line of symmetry. The semiconductor die further includes a first differential power amplifier including a first half circuit and a second half circuit that operate differentially to provide amplification. The first half circuit and the second half circuit are symmetrically connected to the differential ground network. The semiconductor die can further include a second differential power amplifier, and the differential ground network serves to provide isolation between the first differential power amplifier and the second differential power amplifier. | ||||||
| 25 | Headset amplification circuit with error voltage suppression | US14506062 | 2014-10-03 | US09699542B2 | 2017-07-04 | Ulrik Sørensen Wismar; Sejun Kim |
| A headset driver circuit is described which comprises a connector interface. The connector interface comprises a first terminal, a second terminal and a third terminal for establishing respective electrical connections to a first speaker, a microphone and a common ground node of a headphone, earphone or headset, respectively. A first power amplifier is coupled to the first terminal to supply a first audio output signal to the first speaker of the headset. A first switch arrangement comprises a first ground switch is configured for selectively connecting and disconnecting the second terminal and a ground node of the headset driver circuit. The headset driver circuit further comprises a second ground switch configured for selectively connecting and disconnecting the third terminal and the ground node. The headset driver circuit also comprises a differential preamplifier, e.g. a microphone preamplifier, configured to generate a microphone output voltage where the differential preamplifier comprises a first signal input coupled to the second terminal and a second signal input coupled to the third terminal of the connector interface. An error suppression circuit is configured to sense or sample a noise or error voltage at the second terminal when ground connected or the third terminal when ground connected. The error suppression circuit is further configured to add the sensed or sampled noise or error voltage to a predetermined DC bias voltage and generate an error compensated DC bias voltage for the ungrounded one of the second and third terminals of the connector interface. | ||||||
| 26 | Communication over a voltage isolation barrier | US14836424 | 2015-08-26 | US09685923B2 | 2017-06-20 | Anthony B. Candage; Aswath Krishnan Krishnamoorthy |
| A transmitter circuit comprises: an input, an encoder circuit, and a transmitter. During operation, the transmitter circuit receives an input signal. The encoder circuit encodes the received input signal into an encoded signal. The encoder circuit produces the encoded signal: i) to indicate changing states of the input signal, and ii) to include a supplemental transient signal with respect to the received input signal. The transmitter transmits the encoded signal from an output of the first circuit over a link to a second circuit such as a receiver circuit. A receiver decodes the encoded signal to reproduce a rendition of the input signal to control remote power supply circuitry. Presence of the supplemental transient signal in the encoded signal indicates to the receiver circuit that the first circuit actively transmits the output signal even though there may not be any change to a current state of the input signal. | ||||||
| 27 | Methods and circuitry to provide common mode transient immunity | US14835955 | 2015-08-26 | US09548710B2 | 2017-01-17 | Anthony B. Candage |
| Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | ||||||
| 28 | POWER AMPLIFIERS COUPLED IN SERIES | US14589128 | 2015-01-05 | US20160197587A1 | 2016-07-07 | Lars Arknæs-Pedersen |
| A power amplifier system is disclosed, the power amplifier system comprising two power supplies, four amplifier half-bridges arranged as two amplifier full bridges, and an audio processor for establishing control signals for the amplifier full-bridges, where the audio processor and one of the power supplies share a common ground potential, whereas the other power supply has a floating ground; wherein both the amplifier with common ground and the amplifier with floating ground have an amplifier interconnection output and an amplifier output, and wherein the amplifier interconnection outputs are connected, and a load is connected to the amplifier outputs. Further are disclosed amplification methods and PA systems correspondingly. | ||||||
| 29 | METHODS AND CIRCUITRY TO TRIM COMMON MODE TRANSIENT CONTROL CIRCUITRY | US14835973 | 2015-08-26 | US20160065317A1 | 2016-03-03 | Anthony B. Candage |
| Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | ||||||
| 30 | METHODS AND CIRCUITRY TO PROVIDE COMMON MODE TRANSIENT IMMUNITY | US14835955 | 2015-08-26 | US20160065156A1 | 2016-03-03 | Anthony B. Candage |
| Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | ||||||
| 31 | Driver Integrated Circuit | US14122623 | 2012-05-24 | US20140125398A1 | 2014-05-08 | Wen Li; Norio Chujo; Masami Makuuchi; Takehito Kamimura |
| Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2). | ||||||
| 32 | Ground partitioned power amplifier for stable operation | US13310611 | 2011-12-02 | US08604873B2 | 2013-12-10 | Baker Scott; George Maxim; Stephen Franck; Chu Hsiung Ho |
| Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique. | ||||||
| 33 | Electronic device for microwave apparatuses onboard a satellite | US12919219 | 2008-12-16 | US08427221B2 | 2013-04-23 | Christophe Ibert; Cecile Debarge |
| The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment. | ||||||
| 34 | Ground Partitioned Power Amplifier for Stable Operation | US13310611 | 2011-12-02 | US20120139639A1 | 2012-06-07 | Baker Scott; George Maxim; Stephen Franck; Chu Hsiung Ho |
| Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique. | ||||||
| 35 | Differential line receiver with common-mode AC bootstrapping | US363243 | 1994-12-22 | US5568561A | 1996-10-22 | William E. Whitlock |
| A bootstrapped audio line receiver that receives a differential-mode input signal from first and second differential lines and outputs a single-ended signal on an output line. The line receiver includes a differential amplifier and an input amplifier having differential output terminals and differential input terminals. The input amplifier is connected between the differential lines and the differential amplifier. The input amplifier provides a dc current path to a ground terminal while maintaining a high input impedance to ac signals at audio frequencies. The input amplifier also includes an rf filter that removes rf noise without adversely affecting the line receiver's common-mode noise rejection at audio frequencies. In one embodiment, the input amplifier includes two operational amplifiers connected for unity gain and having two bias resistors connected in series between each input terminals of the input amplifier and a ground terminal. A capacitor is connected from the output of each operational amplifier to a node between each set of series connected bias resistors and prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. Thus, the line receiver tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. | ||||||
| 36 | DIFFERENTIAL AUDIO LINE RECEIVER | EP94915853.9 | 1994-04-22 | EP0700597B1 | 2003-03-12 | WHITLOCK, William E. |
| An audio line receiver which tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. The line receiver includes a differential amplifier (50) with input amplifiers (52, 54) on each input of the differential amplifier. The input amplifiers are typically operational amplifiers (A8 or A9) connected for unity gain, but also having two bias resistors (R17 and R19, or R18 and R20) connected in series between the input terminals of the input amplifiers and ground. A capacitor (C1 or C2) connected from the output of the operational amplifier to a node between the two series connected bias resistors prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. | ||||||
| 37 | Amplifier for cancelling noise between circuit systems | EP97107186.5 | 1997-04-30 | EP0809353A2 | 1997-11-26 | Nagata, Mitsuru |
A reference potential difference canceling circuit (3) is provided in a circuit system (11) of a transmitter side to remove noise caused by impedance Z between circuit systems (11, 12) having different reference potentials (13, 14) from a signal, and to transmit the signal. The reference potential (14) of the circuit system (12) of a receiver side is supplied to an input terminal (IN) of the reference potential difference canceling circuit (3), and its output terminal (OUT) is connected to an input terminal of an output amplifier (1) to which a transmitting signal (ei1) is input. A gain of the reference potential difference canceling circuit (3) is set to a reciprocal number of a gain of the output amplifier (1). |
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| 38 | DIFFERENTIAL AUDIO LINE RECEIVER | EP95944208.0 | 1995-12-22 | EP0799524A1 | 1997-10-08 | WHITLOCK, William E. |
| A bootstrapped audio line receiver that receives a differential-mode input signal from first and second differential lines and outputs a single-ended signal on an output line. The line receiver includes a differential amplifier and an input amplifier having differential output terminals and differential input terminals. The input amplifier is connected between the differential lines and the differential amplifier. The input amplifier provides a dc current path to a ground terminal while maintaining a high input impedance to ac signals at audio frequencies. The input amplifier also includes an rf filter that removes rf noise without adversely affecting the line receiver's common-mode noise rejection at audio frequencies. In one embodiment, the input amplifier includes two operational amplifiers connected for unity gain and having two bias resistors connected in series between each input terminals of the input amplifier and a ground terminal. A capacitor is connected from the output of each operational amplifier to a node between each set of series connected bias resistors and prevents the low impedance of the bias resistors from significantly degrading the line receiver's common-mode rejection ratio. Thus, the line receiver tolerates a wide range of balanced and unbalanced source impedances with a minimal deterioration of the line receiver's common-mode rejection ratio. | ||||||
| 39 | Schaltungsanordnung mit einem Multiplexer | EP95112054.2 | 1995-07-29 | EP0757436A1 | 1997-02-05 | Becher, Erwin, Dipl.-Ing. (FH) |
Zur einpoligen Durchschaltung eines von N jeweils eine Signal-Leitung (L1, L2, LN) und jeweils eine Kanalnullpunkt-Leitung (N1, N2, NN) aufweisenden Signalkanälen (K1, K2, KN), wobei N größer als eins ist, auf einen Eingang eines (Differenz-)Verstärkers (1), dessen Schaltung auf einen zugeordneten Schaltungsnullpunkt (SN) bezogen ist, ist ein Eins-aus-N-Multiplexers (2) mit 3N Schaltstrecken (S11, S21, S31, S12, S22, S32, S1N, S2N, S3N) vorgesehen, von denen ein erster Schaltstrecken-Satz (S11, S12, S1N) der Durchschaltung der N Signal-Leitungen (L1, L2, LN) und ein zweiter Schaltstrecken-Satz (S21, S22, S2N) der Weiterschaltung der N Kanalnullpunkt-Leitungen (N1, N2, NN) dient, der jeweilige Eingang der Schaltstrecken eines dritten Schaltstrecken-Satzes (S31, S32, S3N) mit dem jeweiligen Eingang der Schaltstrecken des zweiten Schaltstrecken-Satzes (S21, S22, S2N) verbunden ist, die Ausgänge der letzteren gemeinsam an einem Eingang eines Hilfs-(Differenz-)Verstärkers (3) und die Ausgänge des dritten Schaltstrecken-Satzes (S31, S32, S3N) gemeinsam am Ausgang des Hilfs-(Differenz-)Verstärkers liegen, dessen Schaltung auf den Schaltungsnullpunkt (SN) bezogen ist. |
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| 40 | 위성에 탑재되는 마이크로웨이브 장치용 전자 디바이스 | KR1020107017925 | 2008-12-16 | KR101616255B1 | 2016-04-28 | 이베르크리스또쁘; 드바르쥬세실 |
| 본출원발명은, 마이크로웨이브체인의유도된자화율에대한사양의개선및 유지보수에대한솔루션으로구성된다. 본발명은, 충분히유도된자화율성능을나타내지않는유닛들 (CRF1, CRF2) 사이에단순히하나이상의 180°위상시프터 (PHI) 를부가함으로써, 위성에통합되는디바이스들과같은마이크로웨이브디바이스들의마이크로웨이브체인내에서운반되는기생변조신호 (PAR4) 의상당한감쇠를가능하게하는주 이점을갖는다. 그결과, 본발명은모든보완마이크로웨이브장비내에존재하는전원및 기타 DC/DC 변환기 (SUPP1) 에일반적으로통합되는기생신호의감쇠를담당하는특정한엘리먼트를없앨수 있다. | ||||||
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