This application discloses a circuit system, including an operational amplification circuit. The operational amplification circuit includes N stages of operational amplification units that are cascaded, an input terminal of the 1^st stage of operational amplification unit is an input terminal of the operational amplification circuit, and an output terminal of the N^th stage of operational amplification unit is an output terminal of the operational amplification circuit; an output terminal of the i^th stage of operational amplification unit is connected to an input terminal of the (i+1)^th stage of operational amplification unit, so as to provide an input signal for the (i+1)^th stage of operational amplification unit; and there is a feedback channel from the output terminal of the N^th stage of operational amplification unit to an input terminal of each of the 1^st stage of operational amplification unit to the N^th stage of operational amplification unit, so as to transmit an output signal of the N^th stage of operational amplification unit to the input terminal of each stage of operational amplification unit. In the circuit system in this application, the feedback channel is added to the operational amplification circuit, so that a loop gain of the operational amplification circuit can be increased, and non-ideal features of the operational amplification circuit can be suppressed when a load circuit is driven, thereby improving performance.

An amplifier circuit (AC) for amplifying an output signal (OS) of a capacitive sensor (M) comprises a first input terminal (AIN) to receive the output signal (OS) of the capacitive sensor (M) and a second input terminal (BIN) to receive a bias voltage (Vbias) of the capacitive sensor (M). The amplifier circuit (AC) comprises an amplifier (A) for amplifying the output signal (OS) and a control circuit (CF) arranged in a feedback loop (FL) of the amplifier (A) being configured to control a DC voltage level at an input connection (A1) of the amplifier (A). A bias voltage sensing circuit (BVS) senses a change of the level of the bias voltage (Vbias) at the second input terminal (BIN) and changes the bandwidth of the feedback loop (FL) in dependence on the sensed change of the level of the bias voltage (Vbias).

An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection coupled to a drain terminal to a respective one of the transistors of the first differential stage. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type compared to the transistor pair of the first differential stage, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second complementary differential stage are symmetrically connected to the transistors of the second differential stage such that respective first, second, third and fourth current paths are formed. A pair of output terminals is coupled to the first and the second current path. Gate terminals of the transistors of each of the stages are coupled to a respective pair of input terminals.

An apparatus (100) for performing capacitor amplification in an electronic device may include a first resistor (R_cmp) and a second resistor (R_cmn) that are connected in series and coupled between a set of input terminals of a receiver in the electronic device, a common mode capacitor (C_cm) having a first terminal coupled to a common mode terminal and having a second terminal, and an alternating current-coupled amplifier (110A), hereinafter AC-coupled amplifier, that is coupled between the common mode terminal and the second terminal of the common mode capacitor (C_cm). The first resistor (R_cmp) and the second resistor (R_cmn) may be arranged for obtaining a common mode voltage (V_cm) at the common mode terminal (V_cm) between the first resistor (R_cmp) and the second resistor (R_cmn). In addition, the common mode capacitor (C_cm) may be arranged for reducing a common mode return loss. Additionally, the AC-coupled amplifier (110A) may be arranged for performing capacitor amplification for the common mode capacitor (C_cm).

One example discloses a class-D amplifier apparatus, comprising: an amplifier circuit, having a set of input terminals, a set of output terminals, a quiescent circuit configuration, and an active circuit configuration; an amplifier control device, coupled to the amplifier circuit; wherein the amplifier control device is configured to place the amplifier circuit in the quiescent circuit configuration before measuring a voltage between the set of output terminals; wherein the amplifier control device is configured to add the output terminals voltage from the set of input terminals before placing the amplifier circuit in the active circuit configuration.

A power amplifier of an envelope tracking system is configured to generate an output power with a variable supply voltage that is generated in an envelope tracking path. A signal generation/processing path receives an input signal and processes the input signal to the power amplifier in a main signal processing path. A delay component is configured to generate a delay to the envelope tracking path with respect to the signal generation path. A feedback path is configured to generate a feedback signal from the output of the power amplifier and adjust the delay component or the delay of the delay component during an active transmission or an active transmission mode.

A receiver circuit (10) is disclosed. It comprises a common source or common emitter LNA circuit (30) for amplifying signals at an operating frequency f in the receiver circuit (10). The LNA circuit (30) comprises an input transistor (50) having a first terminal (52), which is a gate or base terminal, operatively connected to an input terminal (32) of the LNA circuit (30), a shunt-feedback capacitor (60) operatively connected between the first terminal (52) of the input transistor (50) and a second terminal (54), which is a drain or collector terminal, of the input transistor (50), and an output capacitor (65) operatively connected between the second terminal (54) of the input transistor (50) and an output terminal (34) of the LNA circuit. The receiver circuit (10) comprises a termination circuit (40) with a current input terminal connected to the output terminal (34) of the LNA circuit (30). The magnitude |Z_in(f) of the input impedance Z_in of the termination circuit (40) at the frequency f is less than 1/10 of the magnitude |Z_CL (f)| =1 /(2πf · C_L) of the impedance Z_CL(f) of the output capacitor (65) of the LNA circuit 30.

The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier (100, 200) comprising an output stage (103) for providing an output current (106) at an output voltage (306), in dependence of an input voltage at a stage input node (262) of the output stage (103), is described. The output stage (103) comprises a first input transistor (270); wherein a gate of the first input transistor (270) is coupled to the stage input node (262) of the output stage (103). Furthermore, the output stage (103) comprises a first diode transistor (271); wherein the first diode transistor (271) is arranged in series with the input transistor (270). In addition, the output stage (103) comprises a pass device (201) configured to provide the output current (106) at the output voltage (306); wherein the first diode transistor (271) and the pass device (201) form a current mirror; wherein a midpoint between the first input transistor (270) and the first diode transistor (271) is coupled to a gate node (308) of the pass device (201). Furthermore, the output stage (103) comprises a second input transistor (370); wherein a gate of the second input transistor (370) is coupled to the stage input node (262) of the output stage (103); wherein the second input transistor (370) is configured to control a voltage level at a replica node (398), in dependence of the input voltage. In addition, the output stage (103) comprises a buffer transistor (312); wherein a gate of the buffer transistor (312) is coupled to the replica node (398) and wherein an input node of the buffer transistor (312) is coupled to the gate node (308), such that the buffer transistor (312) is configured to sink or source a charge current (383, 384) at the gate node (308), subject to the voltage level at the replica node (398) and the voltage level at the gate node (308).

A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample,and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.

The present invention is related to an amplification device, comprising: a device input for receiving a device input signal; an amplifier unit comprising a zero crossing detector unit, an output filter and a lead-lag compensation network. The zero crossing detector unit is arranged for comparing said device input signal with a reference potential and for switching a pulse width modulated detector output signal between a first voltage level and a second voltage level dependent on said comparison. The amplifier unit is arranged for providing an actual device output signal, said actual device output signal being an amplified representation of said device input signal. The amplification device further comprises a device output for providing said actual device output signal, and a control loop bridging said amplifier unit and comprising a forward filter for increasing loop gain for improving a signal-to-noise ratio of said actual device output signal. The forward filter comprises an integrating filter. The amplification device further comprises a deviation detection unit arranged for detecting overmodulation of said amplifier unit, wherein said amplification device is arranged for disabling the functioning of said forward filter for said amplification device upon occurrence of overmodulation of said amplifier unit.