Complex number calculation circuit |
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| 申请号 | EP96115064.6 | 申请日 | 1996-09-19 | 公开(公告)号 | EP0764915A3 | 公开(公告)日 | 1999-01-13 |
| 申请人 | YOZAN INC.; SHARP KABUSHIKI KAISHA; | 发明人 | Zhou Changming,; Shou Guoliang,; Yamamoto Makoto,; Takatori Sunao,; | ||||
| 摘要 | A complex number calculation circuit for directly multiplying a complex number of an analog signal by a digital complex number as a multiplier. A capacitive coupling is used with a plurality of parallel capacitances corresponding to weights of bits of real and imaginary parts of the multiplier. Sign of the multiplier is represented by selection of outputs paths. A complex number calculation circuit for calculating approximated absolute value suitable for an analog architecture. Inverter circuits are used for linear inversion of analog values, and capacitive couplings are use for weighted addition. Analog maximum and minimum circuits with parallel MOSs are used for maximum and minimum calculation. | ||||||
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| 说明书全文 | |||||||
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