子分类：
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | Bit shift circuit | JP22135182 | 1982-12-16 | JPS59111530A | 1984-06-27 | NAKAGAWA YOUICHI |
| PURPOSE:To obtain a high-speed shift in bit unit by using an N-bit bidirectional shift register which can have parallel-in/out and an (N-1)-bit unidirectional shift register which can have parallel-out respectively. CONSTITUTION:An N-bit bidirectional shift register which can have parallel-in/ out is provided together with an (N-1)-bit unidirectional shift register which can have parallel-out, etc. For instance, the data is written to a bit map memory 11 by a central processor CPU via a selector 7 and a bit shift circuit 9. Then the data is displayed at a CRT15 by a display control circuit 12 and a selector 8 via a parallel-serial converter 14. When the data within the memory 11 is shifted, the data is read out by a shift control circuit 13 via the selector 8 with a bit shift carried out by the circuit 9 and then written to the memory 11. | ||||||
| 122 | JPS5921056B2 - | JP14922975 | 1975-12-16 | JPS5921056B2 | 1984-05-17 | JON KURISUCHAN MORAN |
| 123 | Logic unit for placing variable range data field in variable in variable range data bus | JP7420683 | 1983-04-28 | JPS598039A | 1984-01-17 | FUREDERITSUKU HEIZU DEIRU; DANIERU TAJIEN RINGU; RICHIYAADO EDOWAADO MACHITSUKU; DENISU JIEI MAKUBURAIDO |
| 124 | Parallel shifting circuit | JP11258582 | 1982-07-01 | JPS595344A | 1984-01-12 | SUZUKI YOSHITAKE; YAMAUCHI HIROKI; IWATA ATSUSHI |
| PURPOSE:To realize economically two kinds of operating modes of a normalizing shift and an arithmetic shift on an N digit parallel binary data, by holding a parallel shifter in common. CONSTITUTION:An output of an encoder 3 and an absolute value output of an absolute value generating part 4 are inputted to a shift mode selector 5 in case of a normalizing shift and in case of an arithmetic shift, respectively. An output of the shift mode selector 5 is an absolute value display data of 4 bit, and becomes a reference input of two parallel shifters 6, 7. Each output of the parallel shifters 6, 7 is inputted to a shifter output selector 9. A shifter selector 8 refers to positive or negative of a bit shift number of a data, and a shift mode selecting signal, and outputs a control signal to the shifter output selector 9. For instance, if the shift mode is a normalizing mode, an output of the shifter 6 is selected, and if it is an arithmetic mode and the shift number is negative, an output of the shifter 7 is selected. | ||||||
| 125 | Data shifting system | JP2781282 | 1982-02-23 | JPS58144947A | 1983-08-29 | MATSUDA SUSUMU |
| PURPOSE:To reduce the hardware quantity and at the same time to increase the processing speed, by securing an optional shift of data without using a shifting circuit. CONSTITUTION:A certain variable V (00-15) is read out of a variable memory 3, and a shift constant C (00-15) is read out of a constant memory 11. Under such conditions, the variable V (00-15) is multiplied by the constant C (00-15) through a multiplier 5, under the control of a control storage 13. In this case, the higher rank MPY (00-15) of the result MPY (00-31) of the multiplier 5 are all ''0'', and the lower rank MPY (16-31) are coincident with the variable V (00-15). Then the result MPY (00-31) and the contents Acc (00-31) of an accumulator 2 are added together through an adder 6. | ||||||
| 126 | Data shift device | JP2438482 | 1982-02-19 | JPS58142438A | 1983-08-24 | HIRAI TSUNEMITSU; YAMAMOTO NOBORU; YUU KEIICHI |
| PURPOSE:To reduce the amount of hardware, by discriminating the direction of shift, providing a circuit inverting the bit arrangement of data from the higher- order to the lower-order of a data in a register, and shifting left and right only by a unidirectional shift circuit. CONSTITUTION:The direction of shift is checked for the data to be shifted is checked at a shift direction discriminating circuit 12, and when the direction is inverse with a shift circuit 11, the bit arrangement is inverted from the higher- order of the data bit to the lower-order with a data bit inverting circuit 13. This inverted data is shifted for a designated number of digits at the circuit 11, and the bit arrangement is again inverted at a data bit inverting circuit 13, allowing to obtain the shift in the shifted direction. | ||||||
| 127 | Data processor | JP8025681 | 1981-05-27 | JPS57196350A | 1982-12-02 | SUZUKI HISAAKI |
| PURPOSE:To reduce the hardware quantity and improve the processng speed, by adding a simple logical circuit to a general-purpose shift circuit to perform the general shift, the work code extension shift, the half word extension shift, etc. CONSTITUTION:A general-purpose shift circuit 4 consists of the 1st shift circuit 8, the 2nd shift circuit 90 and the 3rd shift circuit 10. The circuit 90 contains a code extending and byte invalidating part 91 in addition to the function of a general shift circuit. For instance, in a word code extension shift process, only the output of a word code extening circuit 17 is set at (1) among the mode indicating signals, and only an AND gate 26 is controlled to be turned on. Then (0) or (1) is set to the output reaching the gate 26 from a register 11 with an indication given from a word address indicating part of the instruction. Thus a right shift of 0- or 32-bits is carried out at the circuit 90. In such way, the general shift, the half word code extension shift, etc. are possible. | ||||||
| 128 | High-speed byte-shifter and its error check circuit | JP20896981 | 1981-12-23 | JPS57168338A | 1982-10-16 | SUTEIBUN MAIKURU OBURAIEN |
| 129 | Operation processing circuit | JP11203180 | 1980-08-13 | JPS5736343A | 1982-02-27 | NAGASAWA TOSHIKATSU |
| PURPOSE:To realize shift functions with less number of gates and to simplify the operation processing circuit, by dividing shift functions into two stages, and performing left and right shift on each byte at the first stage, the left shifts on each bit at the second stage. CONSTITUTION:This operation processing circuit is configured with 8 bits data selecting circits 7 and 8 which perform shifts on each byte, 2 bits data selecting circuits 9, 10, 11 and 12 which perform shifts on each bit, 2 inputs exclusive-OR circuits 14-18, and all adders 20-22. When a leftward n-bit shift is made, the shift is performed so that (n) may become n=B.k+m, 0<=m<=(B-1), where the B is number of shift of 1 byte, the (k) is number of byte, and the number of shift is positive. Moreover, when a rightward n-bit shift is made, the shift is performed so that (n) will become -n=B.k+m, 1<=m<=B, where the number of shift is negative. In this way, shift functions are made with less number of gates and the operation processing circuit is simplified. | ||||||
| 130 | Monolithic integrated semiconductor memory | JP8268580 | 1980-06-18 | JPS567294A | 1981-01-24 | HERUMUUTO RESURAA |
| 131 | JPS5337331U - | JP11955977 | 1977-09-07 | JPS5337331U | 1978-04-01 | |
| 132 | ARITHMETICAL DEVICE, ARITHMETICAL DEVICE ELLIPTICAL SCALAR MULTIPLICATION METHOD AND ELLIPTICAL SCALAR MULTIPLICATION PROGRAM, ARITHMETICAL DEVICE MULTIPLICATIVE OPERATION METHOD AND MULTIPLICATIVE OPERATION PROGRAM, AS WELL AS ARITHMETICAL DEVICE ZERO DETERMINATION METHOD AND ZERO DETERMINATION PROGRAM | EP10861408.2 | 2010-12-27 | EP2660796B1 | 2018-10-31 | NAITO, Yusuke; SAKAI, Yasuyuki |
| An elliptic scalar multiplication kG can be processed in a fixed amount of computation time regardless of the value of a random number k, and timing analysis of the elliptic scalar multiplication kG can be prevented. An initial setting unit 121 sets a specific point G on an elliptic curve in a scalar multiplication variable R. A scalar multiplication unit 122 references a t-bit bit sequence representing a random number k one bit at a time from the most significant bit, and each time one bit is referenced, sets in a work variable R[0] a value obtained by doubling the scalar multiplication variable R, and sets in a work variable R[1] a value obtained by adding the specific point G to the value set in the work variable R[0]. Then, the scalar multiplication unit 122 sets the work variable R[0] in the scalar multiplication variable R if the value of the referenced bit is 0, and sets the work variable R[1] in the scalar multiplication variable R if the value of the referenced bit is 1. A scalar multiple point output unit 123 performs a subtraction of a constant value 2 t G from the scalar multiplication variable R, and outputs a value obtained by the subtraction as a scalar multiple point kG. | ||||||
| 133 | IDENTIFYING GROUPS | EP15890995.2 | 2015-04-30 | EP3289474A1 | 2018-03-07 | NACHLIELI, Hila; FORMAN, George; KESHET, Renato |
| An example method is provided in according with one implementation of the present disclosure. The method comprises generating a group of most frequent elements in a dataset, calculating features of each of the most frequent elements in the dataset, applying a trained model to the features of each of the most frequent elements, and generating a list of predicted relevant elements from the list of most frequent elements. The method further comprises determining at least one element-chain group for each predicted relevant element and a group score for the element-chain-group, ordering a plurality of element-chain groups for the dataset based on the group score for each of the element-chain groups, and identifying a predetermined number of element-chain groups to be outputted to a user. | ||||||
| 134 | ENTROPY SOURCE WITH MAGNETO-RESISTIVE ELEMENT FOR RANDOM NUMBER GENERATOR | EP12798033.2 | 2012-09-17 | EP2758865B1 | 2017-10-18 | JACOBSON, David M.; ZHU, Xiaochun; WU, Wenqing; YUEN, Kendrick Hoy Leong; KANG, Seung H. |
| 135 | DIVISION OPERATIONS FOR MEMORY | EP14860497 | 2014-11-04 | EP3066665A4 | 2017-07-05 | WHEELER KYLE B |
| Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells. | ||||||
| 136 | METHOD AND APPARATUS | EP14736004.4 | 2014-05-30 | EP3005287A2 | 2016-04-13 | URIGUEN, Jose Antonio; DRAGOTTI, Pier Luigi; BLU, Thierry Albert Jean-Louis |
| A signal processing method for estimating a frequency domain representation of signal from a series of samples distorted by an instrument function, the method comprising obtaining the series of samples; obtaining a set of coefficients that fit a set of basis functions to a complex exponential function wherein the set of basis functions comprises a plurality of basis functions each defined by a shifted version of the instrument function in a signal domain; estimating the frequency domain representation of the signal based on the series of samples and the coefficients. This is wherein the estimate of the instrument function is based on a characterisation of the instrument function in the frequency domain at frequencies associated with the complex exponential function. | ||||||
| 137 | BLOCK-BASED CREST FACTOR REDUCTION (CFR) | EP12843913 | 2012-10-26 | EP2783492A4 | 2015-08-12 | AZADET KAMERAN; MOLINA ALBERT; OTHMER JOSEPH H; YU MENG-LIN; PEREZ RAMON SANCHEZ |
| Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak; and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by a minimum phase filter and has a substantially minimum group delay. New peaks associated with peak re-growth are introduced substantially only to the one side of the asymmetric cancellation pulse. The process can optionally rewind by an amount greater than or substantially equal to a group delay of the asymmetric cancellation pulse to address the limited number of pre-cursors that may be present in the asymmetric cancellation pulse. | ||||||
| 138 | Bit depth upscaling of digital audio data | EP10159789.6 | 2010-04-13 | EP2244261A3 | 2011-12-28 | Suzuki, Ryoji; Mori, Yusuke |
A digital audio data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit. The digital data processor includes: a weighted addition circuit which is operable to perform weighted addition on at least the input signal and a signal being time-shifted with respect to the input signal and output as a weighted added input signal; an arithmetic shift circuit which is operable to perform an arithmetic rightward shift operation on the weighted added input signal for a predetermined number of shifts and output as a processed input signal; a bit extension circuit which is operable to attach a predetermined bits to an LSB side of the input signal to generate an intermediate signal of M bits; and an addition circuit which is operable to perform addition of the intermediate signal and the processed input signal so as to generate the M-bit output signal.
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| 139 | Bit-plane extraction operation | EP04102749.1 | 2004-06-16 | EP1607858A1 | 2005-12-21 | The designation of the inventor has not yet been filed |
A programmable data processing apparatus having a bit-plane extraction operation is described, for extracting data from a value of, for example, 32 bits containing 4 bytes, 1a to 1d. Each byte 1a to 1d comprises 8 bits, (a0 - a7, b0 - b7, c0 - c7 and d0 - d7, respectively). The bit-plane extraction operation retrieves one bit from each of these bytes, for example the second bit (a1, b1, c1, d1), which is specified by an argument. The operation involves concatenating these bits (a1, b1, c1, d1) and returning a result value 5. Depending on the particular data processing application, the result value may be bit-reversed to provide a result value 7 (for example, if a bit-reversal is required to deal with endianness, or other reasons). The bit-plane extraction operation can be used as a pre-processing operation in data processing operations such as "sum-of-absolute-differences" in the processing of video data. |
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| 140 | SCHIEBEVORRICHTUNG UND VERFAHREN ZUM VERSCHIEBEN | EP03702419.7 | 2003-01-10 | EP1446711B1 | 2005-10-05 | GAMMEL, Berndt,; KLUG, Franz; KNIFFLER, Oliver |
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