| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | Procédé de rotation d'un mot constitué de "p" éléments binaires et dispositif dans lequel ledit procédé est mis en oeuvre | EP90201960.3 | 1990-07-19 | EP0410515B1 | 1995-01-11 | Leterrier, Benoit; Delaporte, Xavier |
| 2 | CHECK POINTING A SHIFT REGISTER | EP16178017.6 | 2016-07-05 | EP3115888A1 | 2017-01-11 | DAY, Philip |
A hardware structure provides a way for check pointing a main shift register one or more times. The hardware structure includes an extended shift register used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point. An update history shift register has a data position for each check point which is used to store information indicating whether the extended shift register was updated. Check point generation logic derives each check point by selecting a subset of the data elements stored in the extended shift register based on the information stored in the update history shift register.
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| 3 | Procédé de rotation d'un mot constitué de "p" éléments binaires et dispositif dans lequel ledit procédé est mis en oeuvre | EP90201960.3 | 1990-07-19 | EP0410515A1 | 1991-01-30 | Leterrier, Benoit; Delaporte, Xavier |
Le dispositif (1) pour la mise en oeuvre du procédé de l'invention comporte un ensemble de registres (K0, K1, K2, K3 et K4, K5, K6, K7) pour le format global formé d'au moins un registre au format élémentaire, un microprocesseur (8) pour exécuter au moins des instructions de rotation drotie, de rotation gauche et une instruction de transfert d'élément binaire dans un registre de report (C) et une mémoire morte (10) pour contenir des instructions nécessaires pour la mise en oeuvre dudit procédé. Application : carte à microcircuit. |
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| 4 | Word rotation method and apparatus | JP19319490 | 1990-07-23 | JP2901716B2 | 1999-06-07 | BENOWA RETERIERU; ZAUIERU DERAHORUTO |
| The device (1) for the use of the method of the invention comprises an assembly of registers (K0, K1, K2, K3 and K4, K5, K6, K7) for the global format formed by at least one register in the elementary format, a microprocessor (8) for executing at least instructions for right rotation, for left rotation and an instruction for transfer of a binary element into a report register (C) and a read-only memory (10) for containing instructions necessary for the use of the said method. …Application: microcircuit card. … |
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| 5 | Method and device for rotating word | JP19319490 | 1990-07-23 | JPH0368991A | 1991-03-25 | BENOWA RETERIERU; ZABUIERU DERAPORUTO |
| PURPOSE: To efficiently use a storage space by rotating a word, which is formed from binary element bits arranged at the global format position of a register through a carry register and recopying that word into a correspondent register. CONSTITUTION: A word WI of p=28 bits or the like is arranged from a position P4 of i=4, etc., to a position P31 of i+p=31 among global format positions P1-P32 of p+n=32 bits, etc., in registers K0-K3 of RAM of 8 bits, etc. Then, in the case of -0<i-1<n, a binary element A1 of the WI arranged at positions from P(p+1) to P(i+p-1) is recopied to positions from P1 to P(i+p-1) or the like and an element A2 is similarly recopied as well. Even when a value (i) is set on the other conditions, the element is recopied and the preparation is completed. Next, the contents of the registers K0-K3 are rotated through the carry register corresponding to the left and right rotation programs in a ROM and stored in the correspondent register so that the word can be rotated while efficiently using the storage space. COPYRIGHT: (C)1991,JPO | ||||||
| 6 | JPS4890640A - | JP2208672 | 1972-03-03 | JPS4890640A | 1973-11-26 | |
| 7 | High-speed rotator and method comprises an embedded masking | JP2008536674 | 2006-10-04 | JP2009512090A | 2009-03-19 | ダニシュ，アルバート・エヌ; ヌニュス，リンカーン・アール |
| オペランド・ローテータ（１００）及びオペランドを回転させる方法が開示される。 オペランド・ローテータ（１００）は、オペランド・サイズのうちの１つを指示するオペランド・サイズを受け取る第１の入力と、回転量信号を受け取る第２の入力と、複数の制御信号を与える制御出力とを含む。 オペランド・ローテータ（１００）はまた、第１のデコーダ（１０２）の制御出力に結合された第１の入力と、データ・エレメントを受け取る第２の入力と、回転されたデータを与える出力とを有するローテータ（１０４）を含む。 ローテータ（１０４）は、複数の制御信号に応答して、複数のオペランド・サイズのうちの１つに対応するデータ・エレメントの一部を、回転量信号に対応する量だけ回転させる。 | ||||||
| 8 | JPS6367688B2 - | JP15205280 | 1980-10-31 | JPS6367688B2 | 1988-12-27 | SUGYAMA SHIZUO; HAGIWARA YOSHIMUNE; MAEDA SHIGEMICHI; AKAZAWA TAKASHI; KOBAYASHI MASAHITO; KITA YASUHIRO; KIDA JUZO |
| 9 | JPS5421744B1 - | JP13046470 | 1970-12-30 | JPS5421744B1 | 1979-08-01 | |
| 10 | JPS538175B2 - | JP2208672 | 1972-03-03 | JPS538175B2 | 1978-03-25 | |
| 11 | JPS518541B1 - | JP5354270 | 1970-06-22 | JPS518541B1 | 1976-03-17 | |
| An electronic computer having a cyclic, serial access program storing tape memory and a random access memory for storing data. The random access memory also includes an input-output register and portions for storing the address of the next instruction to be executed in the program memory and an indirect address. A predetermined time after transferring an instruction to an instruction register the program memory checks to see if the execution of the instruction has been completed. If it hasn't been, the motion of the tape is stopped until it is completed. Also provided are means for shifting the contents of a selected data memory register. | ||||||
| 12 | 임베딩된 마스킹을 갖는 빠른 회전자와 그 방법 | KR1020087009079 | 2006-10-04 | KR1020080049825A | 2008-06-04 | 누네스,링콘,알.; 데니쉬,알베르트,엔. |
| An operand rotator (100) and method of rotating an operand is disclosed. The operand rotator (100) includes a first decoder (102) with a first input to receive an operand size indicating one of a plurality of operand sizes, a second input for receiving a rotate amount signal and a control output to provide a plurality of control signals. The operand rotator (100) also includes a rotator (104) with a first input coupled to the control output of the first decoder (102), a second input to receive a data element and an output to provide rotated data. The rotator (104) is responsive to the plurality of control signals to rotate portions of the data element corresponding to one of the plurality of operand sizes by an amount corresponding to the rotate amount signal. | ||||||
| 13 | 효율적인 비트 데이터 처리 방법 | KR1020060056996 | 2006-06-23 | KR1020070122040A | 2007-12-28 | 이재욱 |
| A method for efficiently processing bit data is provided to reduce operation quantity as much as at least one cycle per bit by performing an operation of a bit unit after bit data is loaded in order from the top bit to the bottom bit, and improve entire system performance by reducing the operation quantity. A first bit stream is loaded to a register in the order from the top bit to the bottom bit as much as a predetermined size among the data encoded by the bit unit(320). A bit mask defined to extract at least one bit value from the register is initialized. One bit value is extracted from the register by performing an AND operation between the register and the bit mask. The bit mask is operated by a rotation operation to a right side as much as one bit(335). A second bit stream is loaded to the register in the order from the top bit to the bottom bit if a negative flag of a current program status register is set by a first bit value(345). | ||||||
| 14 | CHECK POINTING A SHIFT REGISTER WITH A CIRCULAR BUFFER | US16036104 | 2018-07-16 | US20180321852A1 | 2018-11-08 | Philip Day; Julian Bailey |
| Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register. | ||||||
| 15 | High speed shift register | US180186 | 1980-08-21 | US4379222A | 1983-04-05 | Alan B. Hayter; Bernard L. Reagan, Jr. |
| A high speed shift register device includes first and second shift registers. Odd numbered bits of a word are stored in the first shift register and even numbered bits of the word are stored in the second shift register. The first shift register is clocked by a clock signal, and the second shift register is clocked by the complement of the clock signal. The outputs of the first and second shift registers are alternately shifted by means of a multiplexer to an output conductor. A control input of the multiplexer is connected to the clock input. Data is shifted out of the multiplexer at a rate which is twice the normal shifting rate of each of the first and second shift registers. | ||||||
| 16 | Shift arithmetic device | US52948 | 1979-06-27 | US4345316A | 1982-08-17 | Tatsushi Hirotani; Satoshi Nagata |
| A shift arithmetic device which has a circulating shifter for shifting N-bit information by a specified number of bits and a set circuit for setting logic "O" or "1" in the shifted N-bit information at the bit positions corresponding to the specified number of bits shifted. A memory having stored therein N-bit patterns whose arrangements of logic "0" and "1" sequentially change and a bit arithmetic unit for executing logical processing, for each bit, between N-bit pattern read from an address of the memory corresponding to the number of bits shifted and N-bit information shifted by the circulating shifter. | ||||||
| 17 | Variable digital processor including a register for shifting and rotating bits in either direction | US3588483D | 1968-03-14 | US3588483A | 1971-06-28 | LESNIEWSKI ROBERT J |
| DISCLOSED IS A DATA PROCESSOR INCLUDING A PLURALITY OF CASCADED REGISTERS CONNECTED TOGETHER TO SELECTIVELY PERFORM LEFT AND RIGHT SHIFTS, AS WELL AS RIGHT ROTATION. THE REGISTER STAGES ARE SELECTIVELY CONNECTED TO FEED AND BE RESPONSIVE TO A SINGLE DATA LINE AT EITHER END THEREOF. THE REGISTER STAGES ARE SELECTIVELY CONNECTED WITH PARALLEL DATA LINES TO BE RESPONSIVE TO SIGNALS ON THE DATA LINES. WORKS STORED IN THE REGISTER CAN BE COMBINED WITH WORDS ON THE PARALLEL DATA LINES IN ACCORDANCE WITH LOGIC FUNCTIONS SUCH AS AND, OR, EXCLUSIVE OR, ADDITION, AND SUBTRACTION. THE REGISTER STAGES CAN ALSO COMBINE SIGNALS FROM ONE OF THE SERIAL DATA LINES WITH SIGNALS STORED THEREIN AND FROM THE PARALLEL DATA LINES.
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| 18 | High speed shift register | US3496475D | 1967-03-06 | US3496475A | 1970-02-17 | ARNOLD THOMAS F |
| 19 | Electric signal delay circuit | US24760762 | 1962-12-27 | US3372385A | 1968-03-05 | YOSHIYASU KIKUCHI |
| 20 | Shift register employing logic blocks arranged in closed loop and means for selectively shifting bit positions | US30525663 | 1963-08-29 | US3239764A | 1966-03-08 | VERMA YASH P; SMITH MERLIN G |
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