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Electrically erasable floating gate fet memory cell

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专利汇可以提供Electrically erasable floating gate fet memory cell专利检索,专利查询,专利分析的服务。并且A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.,下面是Electrically erasable floating gate fet memory cell专利的具体信息内容。

1. A memory cell comprising a monocrystalline semiconductor substrate of one conductivity type, a pair of surface impurity regions of the other impurity type in said substrate, a first insulating layer on said substrate extending between said regions, a boron doped polycrystalline semiconductor member on said first layer, a second insulating layer on said member, said second layer comprising boron doped silicon oxide characterized by lower leakage conduction at lower impressed electric field values and higher leakage conduction at higher impressed electric field values, a conductive electrode on said second layer, means for selectively reverse biasing at least one of said regions with respect to said substrate to cause avalanching of the junction between said one region and said substrate to charge said member, and means for applying a voltage pulse to said electrode relative to said substrate to cause leakage conduction through said second layer to discharge said member, the polarity of said voltage pulse on said electrode being opposite to the polarity of charge on said member.
2. The memory cell defined in clain 1 wherein said first layer is thermally grown silicon oxide.
3. The memory cell defined in claim 1 wherein said first layer is about 800A thick and said second layer is about 1,000A thick.
4. The memory cell defined in claim 1 wherein said voltage pulse is at least 1 millisecond in duration.
5. The memory cell defined in claim 1 wherein the capacitance of the capacitor formed by said electrode, said second layer and said member is smaller than the capacitance of the capacitor formed by said member, said first layer and said substrate.
6. The memory cell defined in claim 1 wherein said one conductivity is N-type.
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