Nonvolatile random access memory cell using an alterable threshold field effect write transistor专利检索-随机效应防辐射专利检索查询-专利查询网

Nonvolatile random access memory cell using an alterable threshold field effect write transistor

阅读：568发布：2022-07-03

专利汇可以提供Nonvolatile random access memory cell using an alterable threshold field effect write transistor专利检索，专利查询，专利分析的服务。并且The present invention relates to a nonvolatile random access memory cell having a fixed threshold field effect read transistor, a fixed threshold field effect storage transistor and an alterable threshold field effect write transistor in it. The source electrode of the read transistor is connected to the drain electrode of the storage transistor to sense when the latter transistor is holding a volatile charge on its gate electrode, and the gate electrode of the read transistor and the gate electrode of the write transistor are connected together to consolidate read and write select lines. The drain electrodes of the read transistor and the write transistor are connected together to consolidate read and write lines. The source electrode of the write transistor and the gate electrode of the read transistor are connected together to allow for storage of information on the gate electrode of the latter transistor through the former transistor and to allow for nonvolatile storage into the former transistor of the volatile information in the latter transistor by channel shielding as power is lost to the cell. Storage means is connected to the gate electrode of the write transistor to non-volatilely store the volatile information which is held as a charge or no charge on the gate electrode of the storage transistor, as power is removed from the nonvolatile random access memory cell.，下面是Nonvolatile random access memory cell using an alterable threshold field effect write transistor专利的具体信息内容。

权利要求

1. A nonvolatile random access memory cell, comprising: an alterable threshold field effect write transistor having source, drain and insulated gate electrodes; a fixed threshold field effect storage transistor having source, drain and insulated gate electrodes; a fixed threshold field effect read transistor having source, drain and insulated gate electrodes; the source electrode of the write transistor connected to the gate electrode of the storage transistor; the source electrode of the read transistor connected to the drain electrode of the storage transistor; the drain electrode of the write transistor connected to the drain electrode of the read transistor; the gate electrode of the write transistor connected to the gate electrode of the read transistor; and the source electrode of the storage transistor connected to a chosen potential means.

2. The nonvolatile memory cell of claim 1 wherein the alterable threshold field effect write transistor has two insulator layers therein to store charge therebetween.

3. The nonvolatile memory cell of claim 1 wherein the alterable threshold field effect write transistor is an alterable threshold MNOS field effect write transistor.

4. The nonvolatile memory cell of claim 1 wherein the alterable threshold field effect write transistor is an alterable threshold MAOS field effect write transistor.

5. The nonvolatile memory cell of claim 1 further comprising a store circuit, and means for connecting the gate electrodes of the read and write transistors to the store circuit as power is removed from the nonvolatile memory cell to nonvolatilely store volatile binary information of the storage transistor into the write transistor.

6. The nonvolatile memory cell of claim 1 further comprising an erase circuit, and means for connecting the gate electrodes of the read and write transistors to the erase circuit while power is applied to said nonvolatile memory cell to erase information in the write transistor in anticipation of the nonvolatile storage of new binary information therein.

7. The nonvolatile memory cell of claim 1 further comprising a retrieve circuit, and means for connecting the gate electrodes of the read and write transistors to the retrieve circuit while power is applied to the nonvolatile memory cell to apply a retrieve gate voltage to said gate electrode of the write transistor to retrieve nonvolatilely stored binary information from the write transistor into the storage transistor.

8. The nonvolatile memory cell of claim 7 further comprising a differential amplifier, and means for connecting the drain electrodes of the read and write transistors to the differential amplifier to ssnse for the conduction of the storage transistor at a selected retrieve gate voltage on the gate electrode of the write transistor.

9. A plurality of nonvolatile random access memory cells as in claim 1 arranged in a nonvolatile random access memory array.

10. The nonvolatile random access memory array of claim 9 which is integrated into a semiconductor wafer.

11. The array of nonvolatile memory cells of claim 9 further comprising a store circuit, and means for connecting the store circuit to the gate electrodes of selected read and write transistors to the store circuit as power is removed from said array to nonvolatilely store volatile binary information of storage transistors connected to source electrodes of the selected write transistors into these selected write transistors.

12. The array of nonvolatile memory cells of claim 9 further comprising an erase circuit, and means for connecting the erase circuit to the gate electrodes of selected read and write transistors while power is applied to said array to erase information in the write transistors in anticipation of the nonvolatile storage of new binary information therein.

13. The array of nonvolatile memory cells of claim 9 further comprising a retrieve circuit, and means for connecting the gate electrodes of selected read and write transistors to the retRieve circuit while power is applied to said plurality of nonvolatile memory cells to apply a retrieve gate voltage to gate electrodes of the selected write transistors to retrieve nonvolatilely stored binary information from the selected write transistors onto the gate electrodes of storage transistors connected to the selected write transistors.

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Nonvolatile random access memory cell using an alterable threshold field effect write transistor

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