Control mechanism for producing random-like effects on textile materials
阅读：700发布：2022-07-06
专利汇可以提供Control mechanism for producing random-like effects on textile materials专利检索，专利查询，专利分析的服务。并且A novel circuit, having a number of novel subcombinations thereof, for producing alternate on and off signals which can be used to control one or more clutches which, when activated, produce a slub on a yarn or thread or a space between slubs or for controlling any other suitable circuitry or equipment. This circuit produces an extremely long pseudo-random pattern of effect dispersion to give a true random-like appearance in cloth which is woven from such slub yarns or threads. The minimum length of the spaces and slubs can be independently set on switches which are manually accessible from the exterior of the device and also the ratio between minimum and maximum slub and space widths can be also set on other switches. The circuitry automatically causes the length of the slubs and spaces produced to vary within this range defined between the minimum and maximum values, choosing in a pseudo-random manner successive ones of a fixed number of divisions within that range. In the embodiment described below, that fixed number is 14 divisions between the minimum and maximum length of the slubs and spaces. The circuitry can further be caused to operate in a mode whereby the space or slub length remains constant and another mode in which each of the possible separations in the pseudo-random pattern is produced in succession but not necessarily in order. Similarly, the circuitry can be caused, by manual operation of a switch on the exterior of the device, to produce a slub or space of maximum or minimum length.，下面是Control mechanism for producing random-like effects on textile materials专利的具体信息内容。
1. A circuit for providing pseudorandomly an output signal upon receipt of a given number of input signals comprising: means having a first input for receiving successive input signals and a second input for receiving a program signal, for providing an output signal upon receipt of a given number of input signals, this given number being one of a plurality of numbers and being determined by the program signal received, and means connected to said second input for producing pseudorandomly a succession of different program signals out of a plurality of program signals, each different program signal causing said receiving and providing means to provide its output signal upon receipt of a different number of input signals, eaCh number of which is one of said plurality of numbers including an up and down binary counter having an output connected to said second input and up and down inputs for, increasing the count therein by one whenever an input signal is applied to said up input and decreasing by one the count therein whenever an input signal is applied to said down input and for producing at each of a plurality of counts therein an output signal at its output which is one of said program signals and means for providing said input signals at said up and down inputs, said up and down input signals providing means including: dynamic shift register means having an output connected to its input and also having an enabling input connected to said receiving and providing means for receiving at said enabling input said output signals from said receiving and providing means so that, upon receipt of a given signal from said receiving and providing means, said shift register cyclically provides its contents at its output, means connected to said shift register means for receiving the output of said shift register means, integrating said output, and providing a first output signal when the integrated output exceeds a given level and a second output signal when the integrated output is less than said given level, and up and down logic means connected to said receiving, integrating and providing means and to said binary counter for receiving said first and second output signals from said receiving, integrating and providing means and for applying an input signal to said up input whenever one of said first and second output signals is received and applying an input signal to said down input whenever the other of said first and second signals is received.
2. A circuit as in claim 3 wherein the output of said binary counter is provided on a plurality of binary lines and said up and down logic means includes means connected to said binary lines for causing an input signal to be applied to said up input when the output on each of said binary lines is a logical zero and in input signal to be applied to said down input when the output on each of said binary lines is a logical one.
3. A circuit as in claim 2 further including flip-flop means connected to the output of said providing means for receiving said output signal from said providing means and shifting from a first to second output condition when said output signal is received from said providing means.
4. A circuit as in claim 3 further including: second means having a first input for receiving said successive input signals and a second input for receiving a program signal for providing an output signal upon receipt of a given number of input signals, said given number being one of said plurality of numbers and being determined by the program signal received, second means connected to said second input of said second providing means for producing pseudorandomly a succession of different program signals out of a plurality of said program signals, each said program signal causing said second providing to provide its output signal upon a different number, each of which is one of said plurality of numbers, including a second up and down binary counter having an output connected to said second input of said second providing means and up and down inputs for increasing by one the count therein whenever an input signal is applied to its up input and decreasing by one the count therein whenever an input signal is applied to its down input and for producing at each of a plurality of counts therein an output signal, at said output on a plurality of binary lines, which is one of said program signals, second means connected to said shift register means for receiving an inverted output of said shift register means, integrating said inverted output, and providing a first output signal when the inverted integrated output exceeds a given level and a second output signal when the inverted integrated output is less than said given levEl, and means connecting said second receiving, integrating and providing means to said dynamic shift register means for inverting said output of said shift register means and producing said inverted output signal, and second logic means connected to said second receiving, integrating and providing means and to said second binary counter for receiving said first and second output signals from said second integrating means and for applying an input signal to said up input of said second binary counter whenever one of said first and shcond output signals is received from said second integrating means and applying an input signal to said down input of said second binary counter whenever the other of said first and second output signals is received from said second receiving, integrating and providing means, wherein said flip-flop means is connected to the output of said second providing means for receiving the output signal from said second providing means and shifting from its second condition to its first condition when said output signal from said second receiving and providing means is received and including further logic means connected to said flip-flop means, said first providing means and said second providing means for permitting said first providing means to receive input signals, and preventing said second providing means from receiving input signals, when said flip-flop means is in said first output condition and for permitting said second providing means to receive input signals, and preventing said first providing means from receiving input signals, when said flip-flop means is in said second output condition.
5. A circuit as in claim 4 further including means connected to said flip-flop means for producing thread or yarn having a slub while said flip-flop means is in said second output condition and not producing a slub while said flip-flop means is in said first output condition.
6. A circuit as in claim 4 including first manually operable switch means connected to said binary lines connected to first binary counter having a first position for providing a said program signal to cause said given number to be the maximum of said plurality of numbers, a second position for providing a program signal to cause said given number to be the minimum of said plurality of numbers and a third position not affecting the program signal applied to said first binary counter and second manually operable switch means connected to said binary lines connected to said second binary counter having a first position for providing a program signal to cause said given number to be the maximum of said plurality of numbers, a second position for providing a program signal to cause said given number to be the minimum of said plurality of numbers and a third position not affecting the program signal applied by said second binary counter.
7. A circuit as in claim 6 wherein said logic means which is connected to said first receiving, integrating and providing means and to said first binary counter is also connected to said first providing means to provide an input signal to one of its up and down inputs each time said first providing means provides its output signal and including third manually operable switch means connected to said first providing means, said first binary counter and to said first receiving, integrating and providing means having a first position for causing either said first or second output signal to continuously be applied to said up and down logic means so that each count in said first binary counter is successively produced to cause each of said program signals to appear in succession on the binary lines of said first binary counter, a second position not affecting the count in said first binary counter and a third position preventing the output of said first providing means from being received by said up and down logic means so that the program signal on the binary lines remains the same, wherein said second logic means is Also connected to said second providing means to provide an input signal to one of its up and down inputs each time said second providing means provides an output signal, and fourth manually operable switch means connected to said second providing means, said second binary counter and to said second receiving, integrating and providing means having a first position for causing other said first or second output signal to be continuously applied to said second logic means so that each count in said second binary counter is successively produced to cause each of said program signals to appear in succession on the binary lines of said second binary counter, a second position not affecting the count in said second binary counter and a third position preventing the output of said second providing means from being received by said second logic means so that the program signal on the binary lines of said second binary counter remains the same.
8. A circuit for providing pseudorandomly an output signal upon receipt of a given number of input signals comprising: means having a first input for receiving successive input signals and a second input for receiving a program signal, for providing an output signal upon receipt of a given number of input signals, this given number being one of a plurality of numbers and being determined by the program signal received, means connected to said second input for producing pseudorandomly a succession of different program signals out of a plurality of program signals, each different program signal causing said receiving and providing means to provide its output signal upon receipt of a different number of input signals, each number of which is one of said plurality of numbers, means for producing said inputs signals which are received by said providing means, and input signals producing means including: first counter means for providing at an output a first output signal upon each receipt of a given number of input signals, second counter means connected to the output of said first counter means for receiving successive first output signals from said first counter means, and providing, when an enabling input signal is provided at an enabling input, a second output signal at an output upon each receipt of a given number of said first output signals, third counter means connected to the output of said first counter means for receiving successive first output signals from said first counters means and providing, when an enabling input signal is provided at an enabling input, a third output signal at an output upon each receipt of a predetermined number of said first output signals from said first counter means, flip-flop means connected to the output of said second counter means and to said enabling inputs of said second and third counters, for shifting from a first to a second output condition, whenever said second output signal is provided by said second counter means and said flip-flop means is in said first condition, to provide an enabling input signal to said third counter means and no input enabling signal to said second counter means, and means connected to said flip-flop means for providing a signal for shifting said flip-flop means from said second to said first condition to provide an enabling input signal to said second counter means and no input enabling signal to said third counter means.
9. A method of alternately producing first and second output signals comprising the steps of: producing said first output signal at any one of a plurality of given times in a given time range between a minimum given time and a maximum given time, after said second output signal is produced, determining at which of said given times each said first output signal is produced so that over a time interval during which a large number of first output signals are produced the order of given times is random, and producing said second output signal a predetermined time after said first output siGnal is produced.
10. A method as in claim 9 including the further step of manually varying the length of said given time range.
11. A method as in claim 9 including the further step of manually varying the length of said minimum given time.
12. A method as in claim 9 including the further steps of manually varying the length of said given time range and the length of said minimum given time so as to vary thereby said maximum given time.
13. A method as in claim 9 wherein said step of producing said second output includes the step of producing said second output signal at any one of a plurality of predetermined times in a predetermined time range between a minimum predetermined time and a maximum predetermined time after said first output signal is produced.
14. A method as in claim 9 including the further step of manually varying the length of said predetermined time range.
15. A method as in claim 9 including the further step of manually varying the length of said minimum predetermined time.
16. A method as in claim 9 including the further steps of manually varying the length of said predetermined time range and the length of said minimum predetermined time so as to vary thereby said maximum predetermined time.
17. A method as in claim 16 including the further steps of manually varying the length of said given time range and the length of said minimum given time so as to vary thereby said maximum given time.
18. Apparatus for alternately producing first and second final output signals comprising: means for producing said first final output signal at any one of a plurality of given times, in a given time range between a minimum given time and a maximum given time, after said second final output signal is produced, including means for determining at which of said given times each said first final output signal is produced so that the order of given times is pseudorandom and means connected to said first signal producing means for producing said second final output signal a predetermined time after said first final output signal is produced.
19. Apparatus as in claim 18 further including means for manually varying the length of said given time range.
20. Apparatus as in claim 18 further including means for manually varying the length of said minimum given time.
21. Apparatus as in claim 18 further including means for manually varying the length of said minimum given time and the length of said given time range.
22. Apparatus as in claim 18 wherein said second final output signal producing means includes means for determining at which of said predetermined times each said second final output signal is produced so that the order of predetermined times is pseudorandom.
23. Apparatus as in claim 22 including means for manually varying the length of said minimum given time and the length of said given time range and means for manually varying the length of said minimum predetermined time and the length of said predetermined time range.
24. Apparatus as in claim 22 wherein said first and second final output signals producing means includes a plurality of variable frequency dividers and said given time length and range varying means and said predetermined length and range varying means includes a plurality of manually operable switches having different positions for causing said frequency dividers to vary their frequency.
25. Apparatus as in claim 23 wherein said first and second final output signal producing means includes: first counter means for providing at an output a first output signal upon each receipt of a given number of input signals, second counter means connected to the output of said first counter means for receiving successive first output signals from said first counter means and providing, when an enabling input signal is provided at an enabling input, a second output signal at an output upon each receipt of a given number of said first output signals, third counter means connected to the ouTput of said first counter means for receiving successive first output signals from said first counter means and providing, when an enabling input signal is provided at an enabling input, a third output signal at an output upon each receipt of a predetermined number of said first output signals from said first counter means, flip-flop means connected to the output of said second counter means and to said enabling inputs of said second and third counters for shifting from a first to a second output condition, whenever said second output signal is provided by said second counter means and said flip-flop means is in said first condition, to provide an enabling input signal to said third counter means and no input enabling signal to said second counter means and means connected to said flip-flop means for providing a signal for shifting said flip-flop means from said second to said first condition to provide an enabling input signal to said second counter means and no input enabling signal to said third counter means, and further counter means connected to said first counter means for receiving input signals and providing at an output a first output signal upon receipt of a given number of input signals, the output signals of said further counter means being applied as the input signals to said first counter means, wherein said minimum given time and time range varying means includes first switch means connected to said further counter means for determining and manually varying the given number of input signals, upon receipt of which said further counter means produces its output signal, and second switch means connected to said first, second and third counter means for determining and manually varying said given number of signals, upon receipt of which said second counter means produces its output signal, said given number of input signals upon receipt of which said second counter means produces its output signal and said predetermined number of input signals upon receipt of which said third counter means produces its output signal, and wherein said minimum predetermined time and time range varying means includes third switch means connected to said further counter means for determining and manually varying the given number input signals, upon receipt of which said further counter means produces its output signal, and fourth switch means connected to said first, second and third counter means for determining and manually varying said given number of input signals, upon receipt of which said first counter means produces its output signal, said given number of input signals, upon receipt of which said second counter means produces its output signal and said predetermined number of input signals upon receipt of which said third counter means produces its output signal, and wherein said first and second final output signals producing means further includes: means having a first and second output condition for being in said first output condition while said final first output signal is being produced and being in said second output condition while said final second output signal is being produced, and means connected to said means having a first and second output condition for permitting said first and second switch means to determine and vary and preventing said third and fourth switch means from determining and varying when said means having a first and second output condition is in its first output condition and for permitting said third and fourth switch means to determine and vary and preventing said first and second switch means from determining and varying when said means having a first and second output condition is in its second output condition.
26. Apparatus as in claim 25 wherein said first and second final output signals producing means further includes logic means connecting said second switch means and said fourth switch means to said first counter means and connected to said flip-flop means having, when enabled a first condition, when said flip-flop means is in its first condition and said second or fourth switch means is set in a given position enabling said logic means, said first condition of said logic means causing said first counter means to produce its first output signal upon a first given number and a second condition, when said flip-flop means is in its second position and said second or fourth switch means is in an enabling position, said second condition of said logic means causing said first counter means to produce its first output signal upon a second given number different from said first given number.
27. Apparatus as in claim 25 wherein said first and second final output signals producing means further includes an internal clock for providing a sequence of input signals to said further counter means and means for receiving a succession of input signals from an external source and providing the external signals to said further counter means instead of the signals from said clock.
28. Apparatus as in claim 25 wherein said further counter includes: first counting means for receiving input signals and producing an intermediate signal after each time a given number of input signals, as determined by said first or third switch means, has been received, means connected to said first counting means for resetting said first counting means each time said intermediate signal is produced, second counting means for receiving said intermediate signals, producing a further signal upon a predetermined count therein, as determined by said first or third switch means, and resetting itself upon another count which is not less than said predetermined count, means connecting to said second counting means and having a first and second condition for receiving said further signal and shifting from its first to said second condition upon receipt of said further signal, comparator means connected to said second counting means and to said first and third switch means for producing an enabling signal when the count in said second counting means is equal to the predetermined count, and comparator logic means connected to said comparator means and to said receiving and shifting means for producing the output signal of said first counter means when said enabling signal as produced and said receiving and shifting means is in its second condition including means for applying a reset signal to said second counting means to cause each second counting means to be reset whenever the output signal of said first counter means is produced and for applying a signal to said receiving and shifting means to cause said receiving and shifting means to shift from its first to second condition whenever said first counter means produces its output signal.
29. Apparatus as in claim 25 wherein said given time determining means and said predetermined times determining means includes: first programable means, having a first input connected to said third counter means for receiving as input signals the output signals of said third counter means and connected to said second counter means for receiving as input signals the output signals of said second counter means and having a second input for receiving a program signal, for providing an output signal upon receipt of a given number of input signals, this given number being one of a plurality of numbers and being determined by the program signal received, first pseudorandom means connected to said second input of said first programable means for producing pseudorandomly a succession of different program signals of a plurality of program signals, each program signal causing said first programable means to provide its output signal upon a different number, each of which is one of said plurality of numbers, second programable means, having a first input connected to said third counter means for receiving as input signals the output signals of said third counter means and connected to said second counter means foR receiving as input signals the output signals from said second counter means and having a second input for receiving a program signal upon receipt of a given number of input signals, this given number being one of a plurality of numbers and being determined by the program signal received, second pseudorandom means connected to said second input of said second programable means for producing pseudorandomly a succession of different program signals of a plurality of program signals, each program signal causing said second programable means to provide its output signal upon a different number, each of which is one of a said plurality of numbers, logic means, connected to said means having a first and second output condition, and connecting said second and third counter means to said first and second programable means for permitting output signals from said second and third counter means to be received by said first programable means and preventing output signals from said second and third counter means from being received by said second programable means when said means having a first and second output condition is in said first output condition and for permitting output signals from said second and third counter means to be received by said second programable means and preventing output signals from said second and third counter means from being received by said first programable means when said means having a first and second output condition is in said second output condition, and means connecting said means having a first and second output condition to said first and second programable means so that said means having a first and second output condition shifts from its first to its second condition each time said first programable means provides its output signal and shifts from its second to its first condition each time said second programable means provides its output signal.
30. Apparatus as in claim 29 wherein said first and second pseudorandom means each include an up and down binary counter having an output connected to the second input of the associated pseudorandom means and up and down inputs for increasing by one the count therein whenever an input is applied to said up input and decreasing by one the count therein whenever an input is applied to said down input and for producing at each of a plurality of counts therein an output signal at its output which is one of said program signals and each includes means for providing the input signals to said up and down inputs.
31. Apparatus as in claim 30 wherein said up and down input signals providing means includes: dynamic shift register means having an output connected to its input and also having an enabling input connected to said receiving and providing means for receiving at said enabling input said output signals from said receiving and providing means so that, upon receipt of a given signal from said receiving and providing means, said shift register cyclically provides its contents at its output, means connected to said shift register means for receiving the output of said shift register means, integrating said output, and providing a first output signal when the integrated output exceed a given level and a second output signal when the integrated output is less than said given level, and up and down logic means connected to said receiving, integrating and providing means and to said binary counter for receiving said first and second output signals from said receiving, integrating and providing means and for applying an input signal to said up input whenever one of said first and second output signals is received and applying an input signal to said down input whenever the other of said first and second output signals is received.
32. Apparatus as in claim 31 wherein the output of said binary counter is provided on a plurality of binary lines and said up and down logic means includes means connected to said binary lines for causing an input signal to be applied to saId up input when the output on each of said binary lines is a logical zero and an input signal to be applied to sa1d down input when the output on each of said binary lines is a logical one.
33. Apparatus as in claim 32 further including first manually operable switch means connected to said binary lines connected to first binary counter having a first positon for providing a said program signal to cause said given number to be the maximum of said plurality of numbers, a second position for providing a program signal to cause said given number to be the maximum of said plurality of numbers and a third position not affecting the program signal applied to said first binary counter and second manually operable switch means connected to said binary lines connected to said second binary counter having a first position for providing a program signal to cause said given number to be the maximum of said plurality of numbers, a second position for providing a program signal to cause said given number to be the minimum of said plurality of numbers and a third positon not affecting the program signal applied by said second binary counter.
34. Apparatus as in claim 33 further including third manually operable switch means connected to said first providing means, said first binary counter and to said first receiving, integrating and providing means having a first position for causing either said first or second output signal to continuously be applied to said up and down logic means so that each count in said first binary counter is successively produced to cause each of said program signals to appear in succession on the binary lines of said first binary counter, a second position not affecting the count in said first binary counter and a third position preventing the output of said first providing means from being received by said up and down logic means so that the program signal on the binary lines remains the same, wherein said second logic means is also connected to said second providing means to provide an input signal to one of its up and down inputs each time said second providing means provides an output signal, and fourth manually operable switch means connected to said second providing means, said second binary counter and to said second receiving, integrating and providing means having a first position for causing other said first or second output signal to be continuously applied to said second logic means so that each count in said second binary counter is successively produced to cause each of said program signals to appear in succession on the binary lines of said second binary counter, a second position not affecting the count in said second binary counter and a third position preventing the output of said second providing means from being received by said second logic means so that the program signal on the binary lines of said second binary counter remains the same.
35. Apparatus as in claim 34 further including a driver circuit connected to said means having a first and second output condition comprising: circuit means connected in series with a portion having a first resistance value when a given voltage across said serially connected circuit means and portion is a first polarity so that current flows through said serially connected circuit means and portion in a first direction and so that said current flowing in said first direction is sufficient to store sufficient energy to accomplish said function and having a second and greater resistance value when a given voltage across said serially connected circuit means and portion is the opposite polarity so that current flows through said serially connected circuit means and portion in an opposite direction and so that said current flowing in said opposite direction will not cause sufficient energy to be stored to accomplish said function, and means connected to said circuit means and portion for providing said given voltage of said first polarity across said serially connected portIon and circuit means, when a first input signal is received, so as to produce a voltage of said first polarity across said portion and magnetization of said portion and for providing said given voltage of said opposite polarity across said serially connected circuit means and portion when a second input signal is received so as to produce a smaller voltage of the opposite polarity across said portion so that said portion is demagnetized.
36. Apparatus as in claim 34 further including means connected to said means having a first and second output condition for producing a yarn or thread portion having a slub when said means having a first and second output condition is in its second output condition and producing a yarn or thread portion not having a slub when said means having a first and second condition is in said first condition.
37. Apparatus for alternately producing first and second output signals comprising: means, having a first and second output condition for shifting from said first condition to said second condition when a first input signal is applied and from said second condition to said first condition when a second input signal is applied and for producing said first output signal when in said first condition and said second output signal when in said second condition, means for applying said first input signal to said shifting and producing means a given time after said second input signal is applied to said shifting and producing means, including means for causing said applying means to apply said first input signal at any one of a plurality of different given times after said first signal is applied in a given time range between a minimum given time and a maximum given time and means for determining at which of said given times after each said input signal said first signal is applied so that over a time interval in which a large number of first input signals are applied the order of given times is random, means for manually varying the length of said given time range, and means for applying said second input signal to said shifting and producing means a predetermined time after said first input signal is applied to said shifting and producing means.
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