Dynamic data storage cell
阅读：971发布：2022-07-08
专利汇可以提供Dynamic data storage cell专利检索，专利查询，专利分析的服务。并且A dynamic data storage cell is disclosed that requires only one insulated gate field effect transistor (IGFET) to store binary data. The drain of the FET is connected to a data input line and data is stored at the source node of the transistor by the inherent capacitance between the source diffusion and the substrate. The capacitance of the source electrode is enhanced by forming a heavily doped layer to underlie a portion of the source diffusion. Using the substrate as circuit ground enables the fabrication of an array of transistors for a random access memory wherein the surface area of the semiconductor chip is minimized.，下面是Dynamic data storage cell专利的具体信息内容。
1. A matrix of randomly selectable insulated gate field-effect transistor memory cells integrated on a semiconductor chip comprising in combination; a. a semiconductor substrate of one conductivity type; b. a first set of substantially parallel elongated diffused regions of opposite conductivity type extending from the surface of said substrate and defining respective column data input lines of said matrix; c. a second set of substantially parallel elongated diffused regions of said one conductivity type and having a higher conductivity than said substrate, said second set of regions being spaced from and interleaved in a substantially parallel relationship with said first set of diffused regions; d. a third set of diffused regions of said opposite conductivity type overlying selected spaced apart portions of said second set of diffused regions and forming P-N junctions therewith, each of said third set of regions extending at the surface of said substrate laterally beyond the boundary of the underlying diffused region of said second set, the distance between the boundary of each of said third diffused regions and an adjacent region of said first set of diffused regions defining the channel of an insulated gate field-effect transistor; e. a relatively thick insulating layer overlying said substrate having relatively thin regions in registry with each of said channels; and f. a set of spaced apart elongated conDuctive strips substantially perpendicular to said first set of elongated regions overlying said thin regions of said insulated layers to form gates of the field-effect transistors defining said matrix of memory cells.
2. A matrix of randomly selectable memory cells as set forth in claim 1 wherein said substrate comprises P-type silicon and said first, second and third sets of diffused regions are respectively N+, P+ and N+ types.
3. A matrix of randomly selectable memory cells as set forth in claim 2 wherein said substrate comprises N-type silicon and said first, second and third sets of diffused regions are respectively P+, N+ and P+ types.
4. A dynamic data storage cell comprising: a. a semiconductor wafer of one conductivity type; b. a first diffused region of opposite conductivity type extending from the surface of said wafer and forming one electrode of an insulated gate field-effect transistor; c. a second diffused region of said one conductivity type spaced from said first diffused region; d. a third diffused region of said opposite conductivity type extending from the surface of said wafer into said second diffused region, forming a P-N junction therewith, the boundary of said third diffused region adjacent said first diffused region extending closer to said first region than the corresponding boundary of said second diffused region, said third diffused region forming a second electrode of an insulated gate field-effect transistor; e. a relatively thick insulating layer covering said wafer, said layer having a relatively thin region overlying the surface of said wafer intermediate said first and third diffused regions to form a channel region of an insulated gate field-effect transistor; and f. a metal layer overlying said thin insulated region whereby in response to an electrical signal applied to said conductive layer the amount of electrical charge stored in said one electrode due to the inherent metal-insulator-semiconductor capacitance and P-N junction capacitance between said second and third diffused regions may be varied to represent logic 1 and logic 0 levels.
5. In a dynamic random access memory that includes a matrix of memory cells randomly addressable in response to decoded input signals wherein data is represented in the form of an electrical charge stored by the inherent capacitance of an insulated gate field-effect transistor and P-N junction capacitance, means for refreshing the stored data during each cycle of operation, and means for operating on stored data, the improvement comprising a memory cell requiring only one insulated gate field-effect transistor, said memory cell including a substrate of one conductivity type that serves as circuit ground, spaced apart source and drain diffusions of opposite conductivity type extending to the surface of said substrate, a highly doped diffused region of said one conductivity type underlying the source diffusion and forming a P-N junction therewith to enhance P-N junction capacitance, and a gate formed over a thin insulating region overlying the substrate area between the source and drain diffusions for selectively varying the capacitance stored at the source node of said insulated gate field-effect transistor.
6. A dynamic random access memory as set forth in claim 5 wherein said highly doped diffused region of said one conductivity type is characterized for each column data input line of said matrix as an elongated continuous doped region and wherein said source diffused regions are characterized by a plurality of spaced apart diffused regions overlying portions of said elongated highly doped diffused region at locations where memory cells in the column are desired.
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