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Automatic channel equalization apparatus with data equalization mode adaptor

阅读:463发布:2022-07-18

专利汇可以提供Automatic channel equalization apparatus with data equalization mode adaptor专利检索,专利查询,专利分析的服务。并且Apparatus for automatically equalizing a data channel while data is being transmitted therethrough. This is accomplished by using the data itself, which is randomized, to adjust the receiving apparatus to reduce or eliminate the degrading effects of channel induced inter-symbol interference upon the reception of multilevel pulse amplitude or pulse mode modulation. High data transmission rates are achieved by switching to a data equalization mode of operation following a training period in the conventional system probe equalization mode.,下面是Automatic channel equalization apparatus with data equalization mode adaptor专利的具体信息内容。

1. Communications equipment comprising, in combination: source means for supplying information signals; first randomizing means having given randomizing characteristics and connected to said source means for randomizing the polarity of the information signals from said source means; signal conversion means for transmitting signals through a data link, said transmission means including means for modulating a signal at the transmission end and for demodulating the signal at the receiving end of the data link; means connecting said first randomizing means To said signal conversion means for supplying thereto the amplitude modulated signal; automatic gain control means connected to said signal conversion means for receiving a demodulator output signal therefrom; tapped delay means for providing a transformation of information between input means and parallel output means thereof, said tapped delay means further being connected to receive output signals from said automatic gain control means; second randomizing means having the same randomizing characteristics as said first randomizing means, said second randomizing means including input means and output means; switch means; first multiplying means connected through said switch means to said output means of said second randomizing means and to said parallel outputs of said tapped delay means for multiplying the output signal from said second randomizing means times each of the parallel outputs from said tapped delay means, said first multiplying means providing a plurality of parallel output signals; hold circuit means comprising a plurality of circuits for providing output signals which respond quickly to input signals and decay slowly in the absence of input signals; means connecting said first multiplying means to said plurality of circuits within said hold circuit means whereby each individual circuit is connected to a separate parallel output of said first multiplying means; second multiplying means connected to receive signals from said hold circuit means and from said first tapped delay line means whereby each signal from said tapped delay means is multiplied by a corresponding signal from said hold circuit means, said multiplying means providing parallel outputs indicative of the individual multiplications; summing means for providing a single output signal indicative of the instantaneous summation of all input signals connected to said output means of said multiplying means; data output means for providing a data output signal, connected to said output means of said summing means and connected to said input means of said second randomizing means for providing feedback information thereto; and, digital to analog converter means connected to said data output means and said switch means, said switch means being adapted to connect said first multiplying means alternatively with said second randomizing means and said digital to analog converter means.
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