Analog feedback frequency responsive circuit
阅读：982发布：2022-03-12
专利汇可以提供Analog feedback frequency responsive circuit专利检索，专利查询，专利分析的服务。并且An active analog delay line is utilized as a feedback element to develop output signals as a function of frequency. The analog feedback delay element is arranged to accept the output signals, sample those signals at a periodic clock rate, and to serially pass the sampled signal from stage to stage in order to achieve the amount of delay desired. The output of the delay device is then summed with an input signal to provide a new output signal. The circuit is useful as a sample delay recursive comb type filter and as a selectively controllable oscillator.，下面是Analog feedback frequency responsive circuit专利的具体信息内容。
1. A circuit for developing output signals, said circuit comprising: summation means having at least one input and an output; and means for establishing an output signal at said output of said summation means, said establishing means including means for taking analog samples of said established output signal, means for delaying said analog-sampled signals, said delaying means including an analog delay line having a controllable signal sample propagation rate, and means for applying said delayed output signals to an input of said summation means, thereby establishing said output signal in conjunction with any other input signal to said summation means.
2. The invention set forth in claim 1 further comprising a clock source operable for providing two clock pulses for controlling said signal sample propagation rate, and wherein said analog sample taking means includes means for taking said samples of said establishing output signal under control of both of said clock pulses so as to establish said output signal as a full analog of said input signal.
3. The invention set forth in claim 1 wherein said analog delay line is a bucket brigade device having a plurality of sequentially interconnected stages through which said analog-sampled signals are propagated.
4. The invention set forth in claim 3 further comprising means for selectively controlling the number of said stages through which said analog-sampled signals are propagated.
5. The invention set forth in claim 3 further comprising means for providing periodic clock signals wherein said analog-sampled signals are moved sequentially from stage to stage through said bucket brigade device under control of said periodic clock pulses.
6. The invention set forth in claim 1 further comprising: a plurality of summation means, each having at least one input and an output; and means for establishing an output signal at said output of each said summation means, said establishing means including means for taking analog samples of each said established output signal, means for delaying each said analog-sampled signal, and means for applying each said delayed analog-sampled signal to an input of the corresponding summation means from which said delayed analog-sampled signal was sampled.
7. The invention set forth in claim 6 wherein each said signal establishing means includes an analog delay line having a controllable propagation rate.
8. The invention set forth in claim 7 wherein each said analog delay line comprises a bucket brigade device having a plurality of sequentialLy interconnected stages through which said analog-sampled signals are propagated.
9. The invention set forth in claim 8 further comprising means for selectively controlling the number of said stages through which said analog-sampled signals are propagated.
10. The invention set forth in claim 8 further comprising means for providing periodic clock pulses wherein each said analog-sampled signal is moved from stage to stage through an independent one of said analog delay lines under control of said periodic clock pulses.
11. A filter circuit having input and output terminals comprising: signal summation means having first and second input terminals and an output terminal common with said filter output terminal; means for connecting said filter circuit input terminal to said first terminal of said signal summation means; analog feedback means comprising an analog delay line having a controllable signal sample propagation rate and having input and output terminals, said analog feedback means input terminal being common with said signal summation means output terminal and with said filter circuit output terminal; and means for connecting said output terminal of said analog feedback means to said second input terminal of said signal summation means.
12. The invention set forth in claim 11 wherein said analog delay line comprises a bucket brigade device.
13. The invention set forth in claim 12 further comprising means for providing periodic clock signals wherein the propagation rate of said analog-sampled signals through said bucket brigade deice is controlled by said periodic clock pulses.
14. The invention set forth in claim 11 wherein said analog delay line comprises a plurality of sequential stages through which an analog-sampled signal is propagated and wherein the delay time of said delay line is selectively controllable by means for establishing the number of stages through which a particular analog-sampled signal is propagated.
15. The invention set forth in claim 11 further comprising means for controlling the feedback loop gain from said filter circuit output terminal through said analog delay line and through said summation means back to said filter circuit output terminal.
16. The invention set forth in claim 15 wherein said summation means includes an operational amplifier.
17. The invention set forth in claim 16 wherein said feedback loop gain control means includes a first resistor connected between said analog feedback means output terminal and said second input terminal of said operational amplifier; and a second resistor connected between said second input terminal of said operational amplifier and said output terminal of said operational amplifier.
18. The invention set forth in claim 11 further comprising: a plurality of said filter circuits arranged into groups; means for connecting in common said input terminals of all said filter circuits of the same group; means for providing an input signal to each said common group of input terminals; and means for adjusting said analog feedback line associated with each said filter circuit to give an output response at said output terminal uniquely associated with each said filter circuit only when said input signal is of a certain frequency.
19. The invention set forth in claim 18 wherein all of said analog delay lines are bucket brigade devices having a plurality of delay stages through which analog signals are propagated.
20. The invention set forth in claim 19 wherein all of said bucket brigade delay lines are controllable from a single clock source.
21. The invention set forth in claim 11 wherein the feedback path which extends from said filter circuit output terminal through said analog delay line and through said summation means has an adjustable gain.
22. The invention set forth in claim 21 wherein said gain is adjusted to give a gain of 1 or greater so that said filter circuit becomes an oscillator circuit and will oscillate at a frequency controllable by said analog delay line.
23. The invention set forth in claim 22 further comprising a plurality of said oscillator circuits, means for connecting the outputs of said oscillator circuits together; and means for controlling the analog feedback delay associated with each said oscillator circuit thereby establishing a particular output frequency at said oscillator circuit output.
24. The invention set forth in claim 23 wherein said analog delay line comprises a bucket brigade device having a number of sequential delay stages.
25. The invention set forth in claim 24 wherein said analog control means includes means for controlling the number of said stages of analog feedback delay.
26. An oscillator circuit for developing an output signal having a certain frequency, said circuit comprising: means for establishing an output signal, said establishing means including means for taking analog samples of said established output signal; means for delaying said analog-sampled signal, said means including an analog delay line having a controllable signal sample propagation rate; means for amplifying said delayed analog-sampled signal to establish a loop gain equal to or greater than 1; and means for applying said amplified signal to said output of said circuit thereby establishing said output signal at a frequency controlled by said delaying means.
27. The invention set forth in claim 26 wherein said analog delay line is a bucket brigade device having a plurality of sequentially interconnected stages through which said analog-sampled signals are propagated.
28. The invention set forth in claim 27 further comprising means for selectively controlling the number of said stages through which said analog-sampled signals are propagated.
29. The invention set forth in claim 28 further comprising means for providing periodic clock signals wherein said analog-sampled signals are moved sequentially from stage to stage through said bucket brigade device under control of said periodic clock pulses.
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