CASCADED INTEGRATOR COMB FILTER WITH ARBITRARY INTEGER DECIMATION VALUE AND SCALING FOR UNITY GAIN Patent Application of Shenq-Huey Wang, William D. Elliott, and Xiemei Meng

Technical Field This disclosure relates to digital signal processing applications that require the use of Cascaded Integrator-Comb (CIC) filters. Such filters are often used with over- sampled Analog to Digital Converters (ADC's) to reduce the sample rate of the ADC to the sample rate of interest to the application, and to reduce the aliasing effects generated by the ADC sampling process. Background CIC filters deployed to date are frequently used in digital down-converter applications, as they permit a more efficient hardware implementation than alternate finite-impulse response filters with decimation or a conventional averaging technique. If constrained to powers-of-two decimation values, the CIC can be implemented without multiply or divide operations, but must use very large bit width adders and accumulators for the large values of decimation or interpolation often required in current digital filtering applications. The problem with the current approach is the granularity of the selectable output sample rate. As an example, consider a CIC filter with powers-of two decimation values from 8 to 16,384 (2³ to 2¹⁴). Thus, if the input sample rate is, for example, 16 MHz, the discrete output sample rates available are 2 MHz, 1 MHz, 500 KHz, ... 3.91 KHz, 1.95 KHz, and 0.98 KHz. Since the output sample rate of the CIC is typically input to a digital filter, and to minimize the number of taps required for these follow-on filters, it is highly desirable to improve the granularity of the R values. As an example, an FIR filter with a sharp cutoff frequency at 250 KHz would, with powers-of-two decimation, require a sample rate of 1 MHz and require 507 taps to achieve 80 dB of attenuation with less than 1 dB of ripple. If integer R values were available, the sample rate could be set at 516 KHz (R = 31) and the filter would require only 235 taps, improving filter latency and processing throughput and power requirements. Summary We disclose a CIC digital filter allowing for arbitrary-integer decimation rates. The filter has a shifter connected to its input. The shifter receives a shift control input, where the shift control input is pre-computed as equal to the integer portion of 2 raised to the base-2 logarithm of the gain of the CIC filter. There is a multiplier connected between the input and the shifter. In other embodiments, the multiplier could be connected between the input and the shifter. There are at least four sequentially-connected integrator functions connected to the shifter (or multiplier, as the case may be); a decimation function receiving input from the integrator functions; and at least four sequentially-connected differentiator functions receiving input from the decimation function. The decimation function has a selectable rate equal to any integer between 1 and a number equal to the predetermined maximum decimation value. The multiplier is configured to compute the product of each input data sample by a correction factor; the correction factor being pre-computed as equal to the fractional portion of 2 raised to the base-2 logarithm of the gain of the CIC filter, so as to correct the gain of the CIC filter for decimation values not a power of 2. We also disclose a method of implementing a multi-channel CIC filter for filtering input data samples from a multiple data stream; the multi-channel CIC filter having an input, an output, a shifter, a shift control, a multiplier, a demultiplexer, and a plurality of channels. Each channel has one or more integrator functions, a decimation function, and one or more differentiator functions. The method comprises receiving an input stream of multiplexed data samples; shifting each data sample by a left shift equal to the integer portion of the base-2 logarithm of the CIC filter gain; and, multiplying each so shifted data sample by the fractional portion of the base-2 logarithm of the CIC filter gain. The multiplexed data stream is demultiplexed into two or more data streams. For each data stream, the method includes integrating the shifted and multiplied data sample at least once; decimating the data sample by a pre-determined decimation rate; differentiating the decimated data sample at least once; and, rounding the differentiated data sample to a pre-determined number of bits before outputting the data sample. Drawings Figure 1 illustrates a prior-art four stage CIC filter permitting programmable decimation of up to 16,384 (2 ¹⁴) for decimation values titώt are integer powers of 2. Figure 2 illustrates a CIC filter with arbitrary integer values of decimation up to 131,072. Figure 3 shows an alternate embodiment of the CIC filter receiving a multiplexed data stream and having multiple channels of output. Figure 4 shows representative wave forms for the input to, and output of, the various stages in an example CIC filter. Description Figure 1 illustrates a prior-art four stage CIC filter permitting programmable decimation of up to 16,384 (2¹ ). The shift register at the beginning of the pipeline is used to set a shift value that will maintain unity gain for the programmed decimation value (R) of the filter. This constrains the decimation value to integer powers of two, resulting in 14 discrete decimations settings of 1, 2, 4, 8, ... 16,384. The decimator outputs 1 of R inputs to perform the down-sampling function. The adders and registers are sized to accumulate very large numbers, but can be truncated by a few bits at each stage to eliminate bits that do not affect the output precision. Figure 2 illustrates a CIC filter according to the preferred embodiment with integer values of decimation up to 131,072. This capability is achieved by adding a multiplier (100) before the shift register (110) at the input of the CIC to adjust the gain for values between the powers of two adjustments in the shift register (110). To perform the programming for a particular integer value of R, the gain value in the shifter (110) and the multiplier (100) must equal the drop in dynamic range of the CIC filter per the following equation for a four-stage CIC filter: pyp p • _ 4 _ /Λ integer portion of log (CIC Gain) n fractional portion of log (CIC Gain)

2 would be 2 raised to the integer portion of log₂ (CIC Gain), and the correction factor

3 (105) applied to the multiplier (100) would be 2 raised to the fractional portion of log₂

4 (CIC Gain).

5 As an example, a desired decimation value of R = 36 (not a power of two) in the

6 four-stage filter would generate a shift control value of 47 and a multiplier correction

7 value of 1.24859. (All numbers are in 16-bit two's complement format in the example.)

8 An equivalent multiplier could use floating-point arithmetic, although at the cost of

9 additional hardware complexity. The integrator and differentiator sections (130 and

10 150) are conventionally built of such registers (140) and adders (160), with appropriate

11 feedback or feed-forward as shown. In Fig. 2, the boxes denoted "REG" are the

12 conventional registers (140) used in CIC filters for holding intermediate results, with the

13 outputs truncated as indicated. A rounder (170) after the differentiator section (150)

14 rounds the result to the bit width desired for the output sample The reader will see that

15 if greater attenuation in the stop band is required, additional integrator and differentiator

16 stages could be added to the CIC filter just described. It should also be noted that the

17 input bit width can be any value. The registers and adders must be sized for the

18 maximum input precision desired. One could, for example, input 12 bits and output a

19 precision of 16 bits with a decimation value of at least 256, since the CIC is an

20 averaging filter and will "average out" uniform noise.

21 A multi-channel system with, for example, a single ADC multiplexing conversions from

22 N input channels and then outputting the result to N CIC channels, can be implemented

23 by sharing the multiplier and shifter. The same multiplier and shifter can be used to

24 supply any additional gain correction needed as a result of inaccuracies in the

25 amplification and analog to digital conversion processes. An alternate embodiment

26 having multiple channels of output is depicted in Fig. 3, where the input channel (200)

27 of multiplexed input is multiplied by the correction factor in a single multiplier (100),

28 shifted in a single shifter (230) by a shift correction factor as before, and demultiplexed

29 into separate data channels by a demultiplexer (210).

30 The integrator section ( 130) of the CIC filter in Fig. 2 is clocked at the input

31 data rate. The differentiator section ( 150) is clocked at the input data rate divided by R,

32 the decimation rate. Thus the CIC filter down-converts the input signal sample rate and

33 bandwidth by R. Experiments in a mixed-signal CMOS integrated circuit have shown that the CMOS implementation of this solution is only about 13% larger than the powers-of- two solution for a single channel of input data. However, in a multi-channel system with, for example, a single ADC multiplexing conversions from N input channels and then outputting the result to N CIC channels, the multiplier and shifter can be shared, further reducing the cost, as shown in Fig. 3. Matlab simulations of the CIC for an R value of 36 are shown in Figure 4. Fig. 4A shows the integrator waveforms, and Fig. 4B shows the differentiator (CIC) wave forms for the example filter. These demonstrate that the scaling up by the multiply and shift factors at the front of the CIC results in unity gain at the output; e.g., a 12 bit input cosine waveform produces a dynamic range of 4096 at the output, and the signal is faithfully reproduced. In conclusion, the technique described in this invention shows that any integer decimation value can be chosen as needed to fit the application up to the design maximum of the hardware. The addition of the multiplier provides R maximum - log₂ R additional discrete values of decimation. The design benefits outweigh the 13% or less increased cost of additional hardware. We claim: