This invention relates to an improved solid state image sensor, and more particularly to an improved form of active pixel sensor suitable for implementation in a CMOS integrated circuit.

One well known form of such circuits is that having, for each pixel, a pinned photodiode and four transistors. Known circuits of this kind have limitations.

One is that pinned photodiode pixels have a low output voltage swing due to the large capacitance of the floating diffusion onto which the pinned photodiode charge is transferred. The floating diffusion capacitance is difficult to control accurately as it depends on gate oxide, source diffusion and routing capacitance due to the pixel architecture.

Secondly, the voltage on the floating diffusions must be kept sufficiently high as to maintain full depletion of the photodiode. The voltage on the floating diffusion is however light-signal-dependent, and this imposes a limit on the swing of the pixel which in turn requires that the floating diffusion be reset to as high a voltage as possible. However, the reset voltage is limited by amplifier swings and power supply.

The present invention provides an image sensor having an array of light sensitive pixels, each pixel comprising a photosensitive element which develops a charge in response to incident light, a transfer gate operable to transfer said charge to a sense node, a reset gate, a read gate, and a source follower forming part of an amplifier; each pixel further including a gain capacitor connected to form part of a feedback path across the amplifier controlled by the read and reset gates to reset the pixel to a controlled virtual earth voltage.

From another aspect, the invention provides a method of operating a four-transistor pinned-diode pixel image sensor, the method comprising transferring the photodiode charge onto a gain capacitor connected in feedback across the pixel output amplifier.

Other features and advantages of the invention will be apparent from the description and claims.

An embodiment of the invention will now be described, by way of example only, with reference to the drawings, in which:

• Figure 1(a) is a circuit diagram of part of an image sensor forming one embodiment of the invention;
• Figure 1(b) is an equivalent circuit of the embodiment of Figure 1(a) illustrating the principle of operation;
• Figure 2 is a timing diagram for the circuit of Figure 1;
• Figure 3 illustrates a second embodiment which is a modification of Figure 1;
• Figures 4(a) and 4(b) are views similar to Figures 1(a) and 1(b) of a further embodiment; and
• Figure 5 is a timing diagram illustrating the operation of the circuit of Figure 4.

Figure 1 shows one pixel 10 in a column 12 of a pixel array. It will be understood that the array comprises a number of pixels identical to 10 arranged in a number of columns 12.

The pixel 10 comprises four transistors 14,16,18,20 and one capacitor Ch. The transistors operate as a transfer gate 14, reset gate 16, read gate 18 and source follower 20 similarly to the conventional 4T pinned diode circuit. Photodiode 22 has a capacitance Cpp, and the pixel has a grounded parasitic capacitance shown at Cp.

There are three horizontal lines 24,26, 28 for read, reset and transfer gate. There are two vertical lines 30,32 for the output signal Vout and for node Vx. The pixel 10 forms part of a long-tail pair amplifier with the remainder of the components at 34 at the base of the column.

Figure 1(b) shows the equivalent circuit at a higher level of abstraction. An amplifier 36 (the long-tail pair) has a positive input voltage of VRT. A switched capacitor network is connected to the negative input and to the pixel photodiode 22. The network consists of a reset switch (reset gate 16), a read switch (read gate 18) and a feedback capacitor (Ch).

Operation of the circuit is illustrated in the timing diagram of Figure 2.

To reset the pixel, Read and Reset are pulsed high simultaneously. The amplifier is effectively in unity gain feedback and the pixel is forced to VRT + Voff, where Voff is the offset of the amplifier. The reset line is then set low. Charge injection and sampled thermal noise cause the pixel voltage to depart from the ideal voltage VRT + Voff; however the amplifier still has a feedback path via the capacitor to correct the voltage at the virtual ground. The output voltage of the amplifier will change to (VRT + Voff + Qching/Ch), where Qching is the charge injection from the reset transistor, to correct for these errors and restore the virtual ground to VRT + Voff.

Subsequently, the transfer gate 18 is pulsed high to transfer the pinned photodiode charge onto the charge sensing node Vpix. The output changes by a voltage (VRT = Voff + Qching/Ch + Qpp/Ch), where Qpp is the pinned photodiode charge, to restore the virtual ground to VRT + Voff. The effect of this is that the photodiode charge has been transferred onto the feedback capacitor Ch.

Correlated double sampling must be performed on the output voltage to remove the pixel offset and kT/C noise from the signal. As is well known, this involves storing Vout during reset and during read and differencing the two voltages, and will not be described in detail here.

Note that the system has a gain of Cpp/Ch which is controllable by the value of Ch and is independent of the grounded parasitic capacitance Cp.

The large parasitic associated with source junctions on Vout will help to compensate the amplifier. The other large capacitance is associated with Vx and affects slew rate.

The two main advantages of this mode of operation are:

• 1) The sense node Vpix is always returned to VRT, guaranteeing full depletion of the pinned photodiode.
• 2) The output swing is set by the ratio Cpp/Ch which can be optimised independently of the grounded parasitic Cp.

Turning to Figure 3, this shows a variant of the circuit of Figure 1 which does not require the read switch voltage to be charge pumped. This is because the read switch will always be at the VRT potential at the amplifier input. In Figure 1, the output potential may be as high as AVDD and the NMOS read switch will be conductive only to AVDD-Vtn unless the gate voltage is charge pumped. In Figure 3, VRT can be set to a relatively low voltage and thus the read switch will be conductive under all operating conditions. The capacitance seen at Vout is increased by the bottom plate parasitic of the pixel capacitor of all the pixels connected to that column.

Figure 4 shows another variant. Here an additional vertical line is required to connect each pixel to a column reset switch 40 and an amplify switch 42. The timing of the various switches will be apparent from Figure 5. The amplify switch 42 enables the output voltage to be level shifted to ground at the end of each cycle. This produces an almost rail-to-rail output swing from the amplifier. In contrast, the amplifier in figure 1 will have an output swing from VRT up to AVDD. In Figure 5, the pixel must be reset during a time when it is not being read in order to limit the number of transistors in the pixel to four.

The invention thus provides an image sensor in which the gain of the pixel is defined by a capacitive amplifier with a well-controlled in-pixel capacitance. The amplifier will always reset the pixel to a well-controlled virtual earth voltage, ensuring full depletion of the photodiode under all circumstances. The invention thus makes possible a higher output from a pinned-photodiode pixel, giving improved signal-to-noise and higher sensitivity.