Two-terminal transistor memory utilizing saturation operation
阅读：410发布：2021-08-18
专利汇可以提供Two-terminal transistor memory utilizing saturation operation专利检索，专利查询，专利分析的服务。并且A semiconductor memory cell containing a dual emitter transistor having an uncontacted base is operated as a two-terminal device. A voltage pulse circuit connected to the first emitter, a conduction detector voltage pulse circuit is connected to the second emitter, and a resistor is connected between the first emitter and the collector. Bit information is written into the cell by setting the potential of the base of two values, which represent respectively a ''''1'''' and ''''0.'''' A ''''1'''' is written into the cell by applying appropriate polarity and amplitude voltage pulses to the two emitters to bias the first emitter-base junction to avalanche breakdown and to forward bias the second emitter-base and collector-base junctions so as to cause the transistor to operate in saturation. To read out information previously stored in the cell and write a ''''0'''' into the cell, a positive going voltage pulse is applied by the voltage pulse circuit to the first emitter.，下面是Two-terminal transistor memory utilizing saturation operation专利的具体信息内容。
1. A semiconductor memory cell comprising: a junction transistor having two electrically isolated emitters and an uncontacted base, the potential of which floats at two values which represent, respectively, a ''''1'''' and a ''''0'''' stored in the cell; first circuit means coupled to the transistor for biasing the first emitter-base junction to avalanche breakdown and forwardbiasing the second emitter-base junction and the collector-base junction to set the potential of the base to a first value which is defined as a ''''1;'''' and second means coupled to the transistor for first increasing and then decreasing the potential of the first emitter to set the potential of the base to a second value which is defined as a ''''0.''''
2. A semiconductor cell comprising: a junction transistor having two electrically isolated emitters, a resistor coupled between the first emitter and the collector, and an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to both emitters of said transistor for first adjusting the emitter potentials from initial values to values sufficient to bias the first emitter-base junction to avalanche breakdown, to forward-bias the second emitter-base junction, and to increase the base potential sufficiently to forward-bias the collector-base junction, thereby causing the transistor to conduct in saturation, and then returning the emitter potentials to the initial values, whereby transistor conduction is terminated leaving minority carriers trapped within the transistor for a period of time, whereupon the base potential starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; and a second circuit means coupled to said transistor for first increasing the first emitter potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then decreasing the emitter potential to its initial value, whereby the base potential assumes the ''''0'''' potential.
3. The memory cell of claim 2 wherein said first and second means constitute part of a voltage pulse circuit adapted to supply voltages of different amplitudes and polarities.
4. The memory cell of claim 2 wherein the time required to decrease the first emitter potential and increase the second emitter potential is less than or equal to the period of time in which holes exist in said transistor after saturation conduction is terminated.
5. Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises an NPN junction transistor having two electrically isolated emitters, a resistor coupled between the first emitter and the collector, and an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor memory cell for first adjusting the emitter potentials from initial values to values sufficient to bias the first emitter-base junction to avalanche breakdown, to forward-bias the second emitter-base junction, and to increase the base potential sufficiently to forward-bias the collector-base junction, thereby causing the transistor to conduct in saturation, and then returning the emitter potentials to the initial values, whereby transistor conduction is terminated leaving holes trapped within the transistor for a period of time, whereupon the base potential starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; a second circuit means coupled to a preselected transistor memory cell for first increasing the first emitter potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then decreasing the emitter potential to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.
6. The apparatus of claim 5 wherein said first and second circuit means constitute part of a voltage pulse circuit adapted to supply voltage pulses of different amplitudes and polarities.
7. The semiconductor memory apparatus of claim 5 further comprising conduction detector circuits and wherein the plurality of conduction paths which couple said memory cells to the first and second means also couple the memory cells to the conduction detector circuits.
8. The apparatus of claim 7 wherein the conduction detector circuits are coupled to a reference ground potential.
9. The apparatus of claim 8 wherein said conduction detector circuits are low impedances coupling said second emitters to said reference ground potential.
10. The memory apparatus of claim 5 further comprising electrically activated switches which are coupled to said second emitters, whereby a ''''1'''' or ''''0'''' can be stored in any preselected memory cell without destroying the information stored in any of the other memory cells of said semiconductor memory apparatus.
11. Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises an PNP junction transistor having two electrically isolated emitters, a resistor coupled between the first emitter and the collector, and an uncontacted base, the potential of which floats at two different values which rEpresent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor memory cell for first adjusting the emitter potentials of said transistor from initial values to values sufficient to bias the first emitter-base junction to avalanche breakdown, to forward-bias the second emitter-base junction, and to decrease the base potential sufficiently to forward-bias the collector-base junction, thereby causing the transistor to conduct in saturation, and then returning the emitter potentials to the initial values, whereby transistor conduction is terminated leaving electrons trapped within the transistor for a period of time, whereupon the base potential starts to return to the ''''0'''' potential but instead returns to a different potential defined as the ''''1'''' potential; a second circuit means coupled to a preselected transistor memory cell for first decreasing the first emitter potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then increasing the emitter potential to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.
12. A method for performing a memory function utilizing at least one memory cell having two electrically isolated emitters, a resistor coupled to one of the emitters and the collector, and an uncontacted base, the potential of which floats at two values which represent, respectively, a ''''1'''' and a ''''0'''' stored in the cell comprising the steps of: writing a ''''1'''' into the memory cell by forward-biasing the collector-base junction and the second emitter-base junction and biasing the first emitter-base junction to avalanche breakdown such that the potential of the base is set to a level defined as a ''''1;'''' and reading out information stored in the cell by increasing the potential of the first emitter sufficiently to cause conduction in the transistor if a ''''1'''' is stored in the cell and then decreasing the potential of the first emitter such that the potential of the base is set to a level defined as a ''''0.''''
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