Two-terminal transistor memory utilizing emitter-base avalanche breakdown
阅读：227发布：2021-08-19
专利汇可以提供Two-terminal transistor memory utilizing emitter-base avalanche breakdown专利检索，专利查询，专利分析的服务。并且A semiconductor memory cell containing a single transistor having an uncontacted base is operated as a two-terminal device with a voltage pulse circuit coupled to the collector and a conduction detector circuit coupled to the emitter. Bit information is written into the cell by setting the potential of the base to one of two values, which represent respectively a ''''1'''' and a ''''0.'''' A ''''1'''' is written into the cell by applying a negative polarity voltage pulse to the collector of sufficient amplitude to forward bias the collector-base junction and to bias the emitter-base junction to avalanche breakdown. To read out information previously stored in the cell and to write a ''''0'''' into the cell, a positive going voltage pulse is applied to the collector.，下面是Two-terminal transistor memory utilizing emitter-base avalanche breakdown专利的具体信息内容。
1. A semiconductor memory cell comprising: a junction transistor having an uncontacted base, the potential of which floats at two values which represent, respectively, a ''''1'''' and ''''0'''' stored in the cell; first means coupled to the transistor for forward biasing the collector-base junction and biasing the emitter-base junction to avalanche breakdown to set the potential of the base to a first value which is defined as a ''''1,'''' and second means coupled to the transistor for first increasing and then decreasing the potential of the collector such that the potential of the base is set to a second value which is defined as a ''''0,'''' and conduction occurs within the transistor if, and only if the base was initially at the ''''1'''' potential.
2. A semiconductor memory cell comprising: a junction transistor having an uncontacted base, the potential of which floats at two values which represent, respectively, a ''''1'''' and ''''0'''' stored in the cell; a first circuit means coupled to the collector of said transistor for first decreasing the potential of the collector of said transistor from an initial value to a value that causes the collector-base junction to be forward-biased and the base potential to start to decrease in potential toward a potential greater than that necessary to bias the emitter-base junction to avalanche breakdown, thereby causing the emitter-base junction to operate in avalanche breakdown and preventing the base potential from decreasing further, and then increasing the potential of the collector to its initial value, whereupon the base potential returns to a different potential than the ''''0'''' potential, said different potential being the ''''1'''' potential; and a second circuit means coupled to the collector first increasing the collector potential from an initial value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then decreasing the potential of the collector to its initial value, whereupon the base potential assumes the ''''0'''' potential.
3. The memory cell of claim 2 wherein said first and second means constitute part of a voltage pulse circuit adapted to supply voltage pulses of different amplitudes.
4. The memory cell of claim 2 further comprising a conduction detector circuit coupled to the emitter of the transistor.
5. The memory cell of claim 4 wherein the conduction detector circuit is coupled to a reference ground potential.
6. The memory cell of claim 5 wherein said conduction detector circuit is a low impedance connecting said emitter to said reference ground potential.
7. Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises a junction NPN transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor cell for for first decreasing the potential of the collector of said transistor from an initial value to a value that causes the collector-base junction to be forward-biaSed and the base potential to start to decrease in potential toward a potential greater than that necessary to bias the emitter-base junction to avalanche breakdown, thereby causing the emitter-base junction to operate in avalanche breakdown and preventing the base potential from decreasing further, and then increasing the potential of the collector to its initial value, whereupon the base potential assumes a different potential than the ''''0'''' potential, said different potential being the ''''1'''' potential; a second circuit means coupled to the collector of a preselected transistor memory cell for first increasing the collector potential from an initial value to a value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then decreasing the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.
8. The apparatus of claim 7 wherein said first and second circuit means constitute part of a voltage pulse circuit adapted to supply voltage pulses of different amplitudes and polarities.
9. The semiconductor memory apparatus of claim 6 further comprising conduction detector circuits and wherein the plurality of conduction paths which couple the memory cells to the first and second means also couple the memory cells to the conduction detection circuits.
10. The apparatus of claim 9 wherein the conduction detector circuits are low impedances coupling said emitters to said reference ground potential.
11. The apparatus of claim 10 wherein said conduction detector circuits are low impedances coupling said emitters to said reference ground potential.
12. The apparatus of claim 11 further comprising electrically activated switches which couple said conduction detection circuits to said emitters, whereby a ''''1'''' and ''''0'''' can be stored in or read out of any preselected memory cell without destroying the information stored in any of the other memory cells of said semiconductor memory apparatus.
13. Semiconductor memory apparatus comprising: a plurality of memory cells, each of which comprises a PNP junction transistor having an uncontacted base, the potential of which floats at two different values which represent, respectively, the storage of a ''''1'''' and ''''0'''' in the cell; a first circuit means coupled to a preselected transistor cell for first increasing the potential of the collector of said transistor from an initial value to a value that causes the collector-base junction to be forward-biased and the base potential to start to increase in potential toward a potential greater than that necessary to bias the emitter-base junction to avalanche breakdown, thereby causing the emitter-base junction to operate in avalanche breakdown and preventing the base potential from increasing further, and then decreasing the potential of the collector to its initial value, whereupon the base potential assumes a different potential than the ''''0'''' potential, said different potential being the ''''1'''' potential; a second circuit means coupled to the collector of a preselected transistor memory cell for first decreasing the collector potential from an initial value to a value sufficient to cause transient transistor conduction only if a ''''1'''' is stored in the cell, and then increasing the potential of the collector to its initial value, whereby the base potential assumes the ''''0'''' potential; and a third means forming a plurality of conduction paths coupling said memory cells to said first and second means.
14. A method for performing a memory function utilizing at least one memory cell which comprises a junction transistor having an uncontacted base, the potential of which floats at two values which represent, respectively, a ''''1'''' and a ''''0'''' stored in the cell comprising the steps of: writing a ''''1'''' into the memory cell by forward biasing the collector-base junction and biasing the emitter-base junction to avalanche breakdown such that the base is set to a first potential defined as a ''''1;'''' and reading out information stored in the cell by increasing the potential of the collector sufficiently to cause conduction in the transistor if a ''''1'''' is stored in the cell and then decreasing the potential of the collector such that the base is set to a second potential defined as a ''''0.''''
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