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Decode circuit

阅读：86发布：2023-02-02

专利汇可以提供Decode circuit专利检索，专利查询，专利分析的服务。并且A decode circuit for use in a decoder employing switches such as complementary metal oxide semiconductor (CMOS) field effect transistors, utilizing cascaded (series-connected) switches of one channel type and a pair of cascoded (parallel-connected) switches of the opposite channel type. In the quiescent state the output lines of the decode circuits are clamped to ground to assure that substantially no power is dissipated. When the decoder system is in the select state, the output lines of the unselected decode circuits remain clamped to ground. The circuit has the advantage that it requires only a pair of cascoded switches plus a strobe switch connected in series with the data switches for operation. This results in a considerable savings of the devices required over prior art decode circuits of this type.，下面是Decode circuit专利的具体信息内容。

权利要求

1. In a decoder for decoding multi-bit, parallel channel digital input signals into a plurality of single channel output signals for addressing a memory and including: a plurality of decode circuits, a plurality of input lines selectively connected to said decode circuits for operating a single decode circuit during a decode cycle and a control line for generating a signal determinative of the occurrence of said decode cycle, the improvement wherein each said decode circuit comprises: a set of cascaded field effect transistors of a first channel type; one of said transistors being rendered conductive by said control signal, the remainder of said transistors individually responsive to one of said input signals; said set connected between a first reference potential and said decode circuit output line; a pair of cascoded field effect transistors of a second channel type connected between said output line and a second reference potential; said first cascoded field effect transistor being rendered nonconductive by said control signal; said second cascoded transistor being held conductive by said first reference potential and exhibiting a low transconductance; whereby said first reference potential is connected to said output during a decode cycle when all of said cascaded field effect transistors are operated by said input signals, and said output line is clamped to said second reference potential Through said second cascoded transistor when said decode circuit is unselected.

2. A decoder as in claim 1 wherein said first cascoded transistor exhibits a large transconductance for rapidly discharging said output line when said cascaded transistors are rendered non-conductive.

说明书全文

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Decode circuit

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