Complementary metal oxide semiconductor gate protection diode
阅读：972发布：2023-02-12
专利汇可以提供Complementary metal oxide semiconductor gate protection diode专利检索，专利查询，专利分析的服务。并且Gate protection is given to a complementary metal oxide semiconductor (CMOS) devices against excessive input voltage transients. An input diode which has a lower breakdown voltage than the gate oxide is attached to the input terminal to protect the gate oxide. The input protect diode is formed by diffusing an N+ region which overlaps both a P tube and an N substrate. The diffusion concentrations between the various regions determine the breakdown voltage of the protection diode. The overlapping relationship of the N+ diffusion over the P- tub and N substrate creates a structure which prevents parasitic NPN action.，下面是Complementary metal oxide semiconductor gate protection diode专利的具体信息内容。
1. In combination: a body of semiconductor material of a first conductivity type and having an upper surface; a CMOS device comprising gate, source and drain electrodes in said body; and a voltage sensitive protecting means connectable to said gate electrode for diverting excessive signal voltage from said gate electrode, comprising; a first region extending into said body from said upper surface and being of an opposite conductivity type and forming a first junction with said body, and a second region extending into said body from said upper surface and being of a first conductivity type and being positioned partially overlying said first region and forming a second junction with said first region and an interface with said body; and said second region having a first impurity concentration and said first region having an impurity surface concentration less than said second region for establishing a voltage value above which current flows between said first and second regions.
2. A voltage sensitive protecting means as recited in claim 1, and further comprising; a third region of higher conductivity than said first region and of said same conductivity type and being positioned within said first region for forming a contact enhancement region.
3. A voltage sensitive protecting means as recited in claim 2, and further comprising; means including said third region for connecting said gate electrode to said second region upon current flowing from said second region, through said first region and into said body for diverting excessive signal voltage from said gate electrode.
4. A voltage sensitive protecting means as recited in claim 1, and further comprising: a pAir of spaced third regions of higher conductivity than said first region and being of said same conductivity type and being positioned within said first region for forming contact enhancement regions; and said portion of said semiconductor body positioned between said third regions forming a current limiting resistor.
5. A voltage sensitive protecting means as recited in claim 4, and further comprising: first means including one of said third regions connected to said gate electrode; and second means including another of said third regions for receiving input signal.
6. A CMOS device including a voltage sensitive protecting means, comprising: a body of semiconductor material having an upper surface and being of a first conductivity type and relatively high resistivity for forming a first structure of MOS device; a plurality of spaced first regions of opposite conductivity type material extending into said body from said surface and each of said first regions forming a first junction with said body and said first regions being of relatively high resistivity for forming a second structure of MOS device; a plurality of second regions extending into said body from said upper surface and being of a first conductivity type and relatively low resistivity; a first one of said second regions being positioned partially overlying a first one of said first regions and forming a second junction with said first region and an interface with said body; additional ones of said second regions being positioned in a second one of said first regions as a source and drain region of said second MOS device; a plurality of third regions extending into said body from said upper surface and being of an opposite conductivity type and relatively low resistivity; at least a first one of said third regions being positioned within said first one of said first regions for providing a contact enhancement region for said first one of said first regions; additional ones of said third regions being positioned in said body as a source and drain region of said first MOS device; gate electrodes adhering to said upper surface and positioned between said source and drain regions of said first MOS device and said second MOS device; means for establishing a reference potential at said first one of said second regions; and connecting means interconnecting said first of said third regions and said gate electrodes.
7. A CMOS device as recited in claim 6, wherein: said first of said second regions is annular shaped and terminates said junction between said corresponding first region and said body.
8. A CMOS device as recited in claim 6, wherein: said first MOS device is a P-channel MOS device; and said second MOS device is an N-channel MOS device.
9. A CMOS device as recited in claim 6, wherein: said third region positioned in said first one of said first regions having a first impurity concentration and said first one of said first regions having an impurity surface concentration less than said last mentioned third region for establishing a voltage value above which current flows between said last mentioned first and third regions respectively.
10. A CMOS device as recited in claim 6, wherein: said semiconductor body having a resistivity lying within the range of 1 ohm centimeter to 10 ohms centimeter.
11. The method of fabricating a CMOS semiconductor device comprising the steps of: providing a semiconductor body having an upper surface and being of one type, relatively high resistivity material and being suitable for the formation of a first type MOS device; forming a plurality of spaced first regions of opposite conductivity extending into said body from said surface and each of said first regions forming a first junction with said body and said first regions being of relatively high resistivity type material and being suitable for tHe formation of a second type MOS device; establishing a source and drain region of a second type MOS device within a first of said first regions and simultaneously establishing within a second of said first regions a second region comparable to said source and drain regions and said second region being positioned partially overlying said second one of said first regions and forming a second junction with said first region and an interface with said body; establishing a source and drain region of a first type MOS device within said body and simultaneously establishing within said second of said first regions a third region comparable to said source and drain regions of said first type MOS device for operating as a contact enhancement region for said second of said first regions; forming gate electrodes for said first type MOS device and for said second type MOS device; and forming a metallization layer on said upper surface including at least a conductive path between said gate electrodes and said second region.
| 标题 | 发布/更新时间 | 阅读量 |
|---|---|---|
| 具有偏移消除的读出放大器和存储器装置 | 2020-05-08 | 768 |
| 整合光学辨识功能的显示器 | 2020-05-08 | 310 |
| 用于屏幕上指纹感应的屏幕下光学传感器模块 | 2020-05-08 | 751 |
| 互补金属氧化物半导体(CMOS)晶片中的超声换能器及相关装置和方法 | 2020-05-12 | 138 |
| 一种图像传感器、移动终端及图像拍摄方法 | 2020-05-11 | 461 |
| 一种发光二极管OLED阵列基板及电子设备 | 2020-05-12 | 630 |
| 具有偏移消除的读出放大器和存储器装置 | 2020-05-08 | 411 |
| 一种手持式阴道检测器械 | 2020-05-11 | 548 |
| 一种电流源型四电平直流变换器及其控制方法 | 2020-05-08 | 779 |
| 小型光谱仪模块 | 2020-05-08 | 529 |
高效检索全球专利专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台，是提供专利分析，专利查询，专利检索等数据服务功能的知识产权数据服务商。
我们的产品包含105个国家的1.26亿组数据，免费查、免费专利分析。
分析报告
专利汇分析报告产品可以对行业情报数据进行梳理分析，涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度，系统通过AI智能系统对图表进行解读，只需1分钟，一键生成行业专利分析报告。
互补金属氧化物半导体热门专利
QQ群二维码
意见反馈
意见反馈