Mos bipolar push-pull output buffer
阅读：347发布：2021-12-24
专利汇可以提供Mos bipolar push-pull output buffer专利检索，专利查询，专利分析的服务。并且An output buffer for an MOS integrated logic circuit which utilizes an output stage comprised of a bipolar transistor and an MOS transistor connected in push-pull configuration is described. The output stage is operated by an MOS control circuit which utilizes an inverter stage with an improved capacitive bootstrap switching network to reduce the magnitude of the gate supply voltage required for positive switching. The circuit is characterized by very low input capacitance, and very low output impedance and thus high capacitive drive capability. A unique connection to ground internally of the integrated circuit is also described which comprises a diffusion made at the same time as the emitter diffusion of the bipolar transistor to provide ohmic contact between an overlying conductor and the substrate which then provides the return path to ground.，下面是Mos bipolar push-pull output buffer专利的具体信息内容。
1. An output buffer for an integrated semiconductor logic circuit comprising a field effect output transistor and a bipolar output transistor connected in push-pull configuration to form an output stage, and control means for turning the field effect transistor ''''on'''' and turning the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect transistor ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal, and wherein the output of said buffer is taken from the emitter of said bipolar transistor.
2. The circuit of claim 1 wherein the control means comprises second, third, fourth and fifth MOS transistors, the channel of the second MOS transistor connecting the base of the bipolar transistor to the collector and the gate being connected to the logic input, the gate of the third field effect transistor being connected to the logic input, the channels of the third and fourth transistors being connected in series between the source supply voltage and the gate supply voltage with the common source-drain point being connected to the gate of the output transistor, the channel of the fifth MOS transistor interconnecting the gate of the fourth MOS transistor and the gate supply voltage, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the fourth MOS transistor to the common source-drain point of the third and fourth MOS transistors, the saturation impedance of the third MOS transistor being substantially less than that of the fourth MOS traNsistor.
3. The circuit of claim 2 further characterized by a sixth MOS transistor the channel of which is connected in parallel with the channel of the fourth MOS transistor, the saturation impedance of the sixth MOS transistor being substantially greater than that of the fourth MOS transistor.
4. The circuit of claim 3 further characterized by a seventh MOS transistor connecting the base of the bipolar transistor to the drain supply voltage of the output transistor, the gate of the seventh MOS transistor being connected to the common source-drain of the third and fourth transistors.
5. The control circuit for switching a first MOS transistor ''''on'''' and ''''off'''' in response to a logic control signal comprising second, third, fourth and fifth MOS transistors, the channels of the second and third MOS transistors being connected in series between a source supply voltage and a gate supply voltage with the common drain-source point being connected to the gate of the first MOS transistor, the gate of the third MOS transistor being connected by the channel of the fourth MOS transistor to the gate supply voltage, the gate of the fourth MOS transistor being connected to the gate supply voltage, the channel of the fifth MOS transistor being connected in parallel with the channel of the third MOS transistor, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the third MOS transistor to the common drain-source of the second and third MOS transistors.
6. An output buffer for an integrated semiconductor logic circuit comprising a field effect output transistor and a bipolar output transistor connected in push-pull configuration to form an output stage, and control means for turning the field effect transistor ''''on'''' and turning the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect transistor ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal, and wherein the control means comprises an MOS inverter stage for receiving the logic signal, the output of which is connected to the gate of the output transistor, and a third field effect transistor connecting the base of the bipolar output transistor to the collector, the gate of the third transistor being connected to receive the logic signal.
7. In an integrated semiconductor circuit, the combination comprising a substrate of one conductivity type, a source region and a drain region of the other conductivity type, means coupling the source region to the drain region to form a first field effect transistor, a base region of said other conductivity type having disposed therein an emitter region of said one conductivity type to form a bipolar transistor, means coupling the emitter region to the source region to form an emitter-source junction, and wherein the emitter-source junction is the output of the circuit.
8. The combination of claim 7 further including means coupling the drain region to a first potential and means coupling the collector region to a second potential different from the first potential for providing operating potentials for said semiconductor circuit.
9. The combination of claim 7 further characterized by means forming a control circuit for turning the field effect channel ''''on'''' and the bipolar transistor ''''off'''' in response to one condition of a logic input signal, and for turning the field effect channel ''''off'''' and the bipolar transistor ''''on'''' in response to another condition of the logic input signal.
10. The combination of claim 8 wherein the control circuit includes at least one diffusion of the one conductivity type directly contacting the substrate and a metal conductor in contact with said last mentioned at least one diffusion.
11. The circuit of claim 9 wherein the control means comprises an MOS inverter stAge for receiving the logic signal the output of which is connected to the gate of the output transistor, and a third field effect transistor connecting the base of the bipolar output transistor to the collector, the gate of the third transistor being connected to receive the logic signal.
12. The combination of claim 9 wherein the control circuit comprises second, third, fourth and fifth MOS transistors, the channels of the second and third MOS transistors being connected in series between a source supply voltage and a gate supply voltage with the common drain-source point being connected to the gate of the first MOS transistor, the gate of the third MOS transistor being connected by the channel of the fourth MOS transistor to the gate supply voltage, the gate of the fourth MOS transistor being connected to the gate supply voltage, the channel of the fifth MOS transistor being connected in parallel with the channel of the third MOS transistor, the gate of the fifth MOS transistor being connected to the gate supply voltage, and a capacitor coupling the gate of the third MOS transistor to the common drain-source of the second and third MOS transistors.
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